[Intel-gfx] [PATCH 18/21] drm/i915: disable platform support for vGPU huge gtt pages

[Matthew Auld]

Currently gvt gtt handling doesn't support huge page entries, so disable
for now.

Suggested-by: Zhenyu Wang <zhenyuw at linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 74ad006cac15..c171511d3251 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4871,6 +4871,15 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
 
+	/* If the guest supports the 48b PPGGT, then we need to fallback to 4K
+	 * pages, since gvt gtt handling doesn't support huge page entries - we
+	 * need to check either hypervisor mm can support huge guest page or
+	 * just do emulation in gvt.
+	 */
+	if (USES_FULL_48BIT_PPGTT(dev_priv) && intel_vgpu_active(dev_priv))
+		mkwrite_device_info(dev_priv)->page_size_mask =
+			I915_GTT_PAGE_SIZE_4K;
+
 	dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
 
 	if (!i915.enable_execlists) {
-- 
2.13.3