[Intel-gfx] [PATCH 09/15] drm/i915: disable GTT cache for 2M/1G pages

[Chris Wilson]

On Wed, May 31, 2017 at 07:52:04PM +0100, Matthew Auld wrote:
> When SW enables the use of 2M/1G pages, it must disable the GTT cache.
> 
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 936eef1634c7..496b64f65eb2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8195,10 +8195,10 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  	/*
>  	 * WaGttCachingOffByDefault:bdw
> -	 * GTT cache may not work with big pages, so if those
> -	 * are ever enabled GTT cache may need to be disabled.
> +	 * The GTT cache must be disabled if the system is planning to use
> +	 * 2M/1G pages.
>  	 */
> -	I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
> +	I915_WRITE(HSW_GTT_CACHE_EN, 0);
>  
>  	/* WaKVMNotificationOnConfigChange:bdw */
>  	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
> @@ -8474,10 +8474,10 @@ static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
>  	gen8_set_l3sqc_credits(dev_priv, 38, 2);
>  
>  	/*
> -	 * GTT cache may not work with big pages, so if those
> -	 * are ever enabled GTT cache may need to be disabled.
> +	 * The GTT cache must be disabled if the system is planning to use
> +	 * 2M/1G pages.
>  	 */

Cherryview doesn't support 48bit ppgtt so isn't using huge pages.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre