[Intel-gfx] [PATCH 3/7] drm/i915: Use a loop for the "three times for luck" DPLL procedure

[Jani Nikula]

On Thu, 01 Jun 2017, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> The magic "enable the  DPLL three times" sequence feels like it
> deserves a loop.

I think the copy-paste unrolled loop is more fun. ;)

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4e3c64ed4131..2b112229b5b2 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1550,6 +1550,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	i915_reg_t reg = DPLL(crtc->pipe);
>  	u32 dpll = crtc->config->dpll_hw_state.dpll;
> +	int i;
>  
>  	assert_pipe_disabled(dev_priv, crtc->pipe);
>  
> @@ -1596,15 +1597,11 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
>  	}
>  
>  	/* We do this three times for luck */
> -	I915_WRITE(reg, dpll);
> -	POSTING_READ(reg);
> -	udelay(150); /* wait for warmup */
> -	I915_WRITE(reg, dpll);
> -	POSTING_READ(reg);
> -	udelay(150); /* wait for warmup */
> -	I915_WRITE(reg, dpll);
> -	POSTING_READ(reg);
> -	udelay(150); /* wait for warmup */
> +	for (i = 0; i < 3; i++) {
> +		I915_WRITE(reg, dpll);
> +		POSTING_READ(reg);
> +		udelay(150); /* wait for warmup */
> +	}
>  }
>  
>  /**

-- 
Jani Nikula, Intel Open Source Technology Center