[Intel-gfx] [PATCH 6/6] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

[Rodrigo Vivi]

Patches merged to dinq.
Thanks for the reviews!

On Jun 2, 2017, 1:07 PM -0700, Rodrigo Vivi <rodrigo.vivi at intel.com>, wrote:
> Panel Power sequences for CNP is similar to Broxton,
> but with only one sequencer.
>
> Main difference from SPT is that PP_DIVISOR was removed
> and power cycle delay has been moved to PP_CONTROL.
>
> v2: Add missed pp_div write, that is now part of PP_CONTROL[8:4]
> as on Broxton. (Found by DK)
>
> v3: Improve commit message. (By DK)
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com
> Cc: Jani Nikula <jani.nikula at intel.com
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com
> Reviewed-by: Clinton Taylor <clinton.a.taylor at intel.com
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com
> ---
> drivers/gpu/drm/i915/intel_dp.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 58dca87..db51338 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -798,7 +798,7 @@ static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
> regs->pp_stat = PP_STATUS(pps_idx);
> regs->pp_on = PP_ON_DELAYS(pps_idx);
> regs->pp_off = PP_OFF_DELAYS(pps_idx);
> - if (!IS_GEN9_LP(dev_priv))
> + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv))
> regs->pp_div = PP_DIVISOR(pps_idx);
> }
>
> @@ -5099,7 +5099,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
> - if (!IS_GEN9_LP(dev_priv)) {
> + if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) {
> I915_WRITE(regs.pp_ctrl, pp_ctl);
> pp_div = I915_READ(regs.pp_div);
> }
> @@ -5117,7 +5117,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK)
> PANEL_POWER_DOWN_DELAY_SHIFT;
>
> - if (IS_GEN9_LP(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK)
> BXT_POWER_CYCLE_DELAY_SHIFT;
> if (tmp > 0)
> @@ -5274,7 +5274,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> /* Compute the divisor for the pp clock, simply match the Bspec
> * formula. */
> - if (IS_GEN9_LP(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> pp_div = I915_READ(regs.pp_ctrl);
> pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
> @@ -5300,7 +5300,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_GEN9_LP(dev_priv))
> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> I915_WRITE(regs.pp_ctrl, pp_div);
> else
> I915_WRITE(regs.pp_div, pp_div);
> @@ -5308,7 +5308,7 @@ static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
> I915_READ(regs.pp_on),
> I915_READ(regs.pp_off),
> - IS_GEN9_LP(dev_priv) ?
> + (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ?
> (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
> I915_READ(regs.pp_div));
> }
> --
> 1.9.1
>
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