[Intel-gfx] [PATCH 1/8] drm/i915: Implement .get_format_info() hook for CCS

[Ville Syrjälä]

On Wed, Jun 07, 2017 at 03:24:58PM +0100, Daniel Stone wrote:
> Hi,
> 
> On 7 June 2017 at 13:53, Ville Syrjälä <ville.syrjala at linux.intel.com> wrote:
> > On Wed, Jun 07, 2017 at 12:44:47PM +0100, Daniel Stone wrote:
> >> /*
> >>  * We don't require any
> >>  * CCS block size alignment of the fb under the assumption that the
> >>  * hardware will handle things correctly of only a single pixel
> >>  * gets touched. The compression should be lossless so any garbage
> >>  * pixels as part of the same block shouldn't cause visual artifacts.
> >>  */
> >
> > The alignment requirement is gone in upstream, hence my latest CCS
> > stuff doesn't have the valign/halign stuff anymore.
> 
> Oh sorry, I'd missed the hsub requirement dropping out. That's fine then.
> 
> > Anyways, I'll have to revisit the the offsets[] thing because people
> > didn't like my original linear offset idea, and it doesn't match what
> > userspace already does.
> 
> I'm still really confused about this. Your patches implement a linear
> byte offset. The last time it came up on IRC, all four of myself, Ben,
> Jason, and you, agreed that linear byte offsets were the only thing
> which made sense. The Mesa patchset that's been sent out a couple of
> times and is now in Jason's hands use linear offsets. If everything
> (kernel, Mesa) uses linear offsets, and everyone (the four of us in
> the discussion) wants linear offsets - why revisit?

Mesa doesn't use linear offsets. Or at least it didn't when I last
looked.

-- 
Ville Syrjälä
Intel OTC