[Intel-gfx] Power management test in DP compliance suite

[Ville Syrjälä]

On Thu, Jun 08, 2017 at 04:36:25PM +0000, Navare, Manasi D wrote:
> On Thu, Jun 08, 2017 at 12:59:23AM +0000, Navare, Manasi D wrote:
> > Hi,
> > 
> > I am executing the DP compliance test suite and the only test 
> > currently failing with the drm-tip  + my patch  
> > (https://patchwork.freedesktop.org/series/25191/)
> > Is the power management test (4.4.3) where it expects the source DUT to go into Power state D3 by setting DPCD register 0x600 to 2 as requested by the test GUI and then exit to normal operation by writing 1 to that DPCD register.
> > 
> > I see that in the code intel_dp_sink_dpms() with DPMS_OFF will set that register to 2 and then with DPMS on it sets it to 1, but since that happens only during encoder disable and enable, I am not sure how it will happen through this test.
> > 
> > Any thoughts? Please refer to the section 4.4.3 in the CTS spec.
> 
> There doesn't seem to support for automated test request for this stuff, so it has to be done manually. What we should do in the test application is ConnectorSetProperty(DPMS, OFF) + ConnectorSetProperty(DPMS, ON).
> 
> But DPR 120 does not send a special power management test request, so when should the app set DPMS property OFF and ON?

Yes, so presumably the user has to manually do it.

> Is DPMS a property exposed through Connector properties?

Yes. See kmstest_connector_dpms_something() in igt.

-- 
Ville Syrjälä
Intel OTC