[Intel-gfx] [PATCH 6/8] drm/i915: Add NV12 as supported format for primary plane

[Ville Syrjälä]

On Wed, Jun 07, 2017 at 04:11:46PM +0530, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru at intel.com>
> 
> This patch adds NV12 to list of supported formats for
> primary plane
> 
> v2: Rebased (Chandra Konduru)
> 
> v3: Rebased (me)
> 
> Link: https://patchwork.kernel.org/patch/6426201/
> Signed-off-by: Chandra Konduru <chandra.konduru at intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti at intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 22 +++++++++++++++++++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f62df27..300f589 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -87,6 +87,18 @@ static bool is_mmio_work(struct intel_flip_work *work)
>  	DRM_FORMAT_VYUY,
>  };
>  
> +static const uint32_t skl_primary_formats_with_nv12[] = {

I would drop the _with_. It just makes things longer without adding
anything extra.

> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_NV12,
> +};

Where are the packed YUV formats?

> +
>  /* Cursor formats */
>  static const uint32_t intel_cursor_formats[] = {
>  	DRM_FORMAT_ARGB8888,
> @@ -13968,9 +13980,13 @@ void intel_plane_destroy(struct drm_plane *plane)
>  	primary->check_plane = intel_check_primary_plane;
>  
>  	if (INTEL_GEN(dev_priv) >= 9) {
> -		intel_primary_formats = skl_primary_formats;
> -		num_formats = ARRAY_SIZE(skl_primary_formats);
> -
> +		if (pipe == PIPE_A || pipe == PIPE_B) {
> +			intel_primary_formats = skl_primary_formats_with_nv12;
> +			num_formats = ARRAY_SIZE(skl_primary_formats_with_nv12);
> +		} else {
> +			intel_primary_formats = skl_primary_formats;
> +			num_formats = ARRAY_SIZE(skl_primary_formats);
> +		}
>  		primary->update_plane = skylake_update_primary_plane;
>  		primary->disable_plane = skylake_disable_primary_plane;
>  	} else if (INTEL_GEN(dev_priv) >= 4) {
> -- 
> 1.9.1
> 
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-- 
Ville Syrjälä
Intel OTC