[Intel-gfx] [PATCH v8 3/6] drm/i915/gvt: Frame buffer decoder support for GVT-g

[Zhenyu Wang]

On 2017.06.09 14:50:39 +0800, Xiaoguang Chen wrote:
> decode frambuffer attributes of primary, cursor and sprite plane
> 
> Signed-off-by: Xiaoguang Chen <xiaoguang.chen at intel.com>

...

> +/**
> + * intel_vgpu_decode_primary_plane - Decode primary plane
> + * @vgpu: input vgpu
> + * @plane: primary plane to save decoded info
> + * This function is called for decoding plane
> + *
> + * Returns:
> + * 0 on success, non-zero if failed.
> + */
> +int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
> +	struct intel_vgpu_primary_plane_format *plane)
> +{
> +	u32 val, fmt;
> +	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> +	int pipe;
> +
> +	pipe = get_active_pipe(vgpu);
> +	if (pipe >= I915_MAX_PIPES)
> +		return -ENODEV;
> +
> +	val = vgpu_vreg(vgpu, DSPCNTR(pipe));
> +	plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
> +	if (!plane->enabled)
> +		return -ENODEV;
> +
> +	if (IS_SKYLAKE(dev_priv)) {
> +		plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
> +		_PLANE_CTL_TILED_SHIFT;
> +		fmt = skl_format_to_drm(
> +			val & PLANE_CTL_FORMAT_MASK,
> +			val & PLANE_CTL_ORDER_RGBX,
> +			val & PLANE_CTL_ALPHA_MASK,
> +			val & PLANE_CTL_YUV422_ORDER_MASK);
> +		plane->bpp = skl_pixel_formats[fmt].bpp;
> +		plane->drm_format = skl_pixel_formats[fmt].drm_format;
> +	} else {
> +		plane->tiled = !!(val & DISPPLANE_TILED);
> +		fmt = (val & DISPPLANE_PIXFORMAT_MASK) >> _PRI_PLANE_FMT_SHIFT;
> +		plane->bpp = bdw_pixel_formats[fmt].bpp;
> +		plane->drm_format = bdw_pixel_formats[fmt].drm_format;
> +	}
> +
> +	if (!skl_pixel_formats[fmt].bpp	&& !bdw_pixel_formats[fmt].bpp) {
> +		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
> +		return -EINVAL;
> +	}

Is this correct? shouldn't be plane->bpp as last time comment?

> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 55e3010..400759f 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -161,6 +161,12 @@ extern "C" {
>  #define DRM_FORMAT_YUV444	fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
>  #define DRM_FORMAT_YVU444	fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
>  
> +/*
> + * Intel GVT-g plane format definition
> + */
> +#define DRM_FORMAT_XRGB161616_GVT  fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
> +#define DRM_FORMAT_XBGR161616_GVT  fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
> +
>  

This should be a seperate patch and not need GVT postfix for format definition.

-- 
Open Source Technology Center, Intel ltd.

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