[Intel-gfx] [PATCH 5/5] drm/i915: Add support for the YCbCr COLOR_RANGE property
Sharma, Shashank
shashank.sharma at intel.com
Thu Jun 15 13:37:59 UTC 2017
Reviewed-by: Shashank Sharma <shashank.sharma at intel.com>
Regards
Shashank
On 6/9/2017 2:03 AM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Add support for the COLOR_RANGE property on planes. This property
> selects whether the input YCbCr data is to treated as limited range
> or full range.
>
> On most platforms this is a matter of setting the "YUV range correction
> disable" bit, and on VLV/CHV we'll just have to program the color
> correction logic to pass the data through unmodified.
>
> Cc: Jyri Sarha <jsarha at ti.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_display.c | 9 ++++++++-
> drivers/gpu/drm/i915/intel_sprite.c | 12 ++++++++++--
> 3 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bac3ec378b6e..6b16b25ba96f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5604,6 +5604,7 @@ enum {
> #define _DVSACNTR 0x72180
> #define DVS_ENABLE (1<<31)
> #define DVS_GAMMA_ENABLE (1<<30)
> +#define DVS_YUV_RANGE_CORRECTION_DISABLE (1<<27)
> #define DVS_PIXFORMAT_MASK (3<<25)
> #define DVS_FORMAT_YUV422 (0<<25)
> #define DVS_FORMAT_RGBX101010 (1<<25)
> @@ -5672,6 +5673,7 @@ enum {
> #define _SPRA_CTL 0x70280
> #define SPRITE_ENABLE (1<<31)
> #define SPRITE_GAMMA_ENABLE (1<<30)
> +#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1<<28)
> #define SPRITE_PIXFORMAT_MASK (7<<25)
> #define SPRITE_FORMAT_YUV422 (0<<25)
> #define SPRITE_FORMAT_RGBX101010 (1<<25)
> @@ -5863,6 +5865,7 @@ enum {
> #define _PLANE_CTL_3_A 0x70380
> #define PLANE_CTL_ENABLE (1 << 31)
> #define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
> +#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> #define PLANE_CTL_FORMAT_MASK (0xf << 24)
> #define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
> #define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
> @@ -5926,6 +5929,7 @@ enum {
> #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
> #define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
> #define PLANE_COLOR_PIPE_GAMMA_ENABLE (1 << 30)
> +#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
> #define PLANE_COLOR_PIPE_CSC_ENABLE (1 << 23)
> #define PLANE_COLOR_CSC_MODE_BYPASS (0 << 17)
> #define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ba3ad0e26043..6fe6e67eeefc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3324,6 +3324,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>
> if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> plane_ctl |= PLANE_CTL_YUV_CSC_FORMAT_BT709;
> +
> + if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
> }
>
> plane_ctl |= skl_plane_ctl_format(fb->format->format);
> @@ -3352,6 +3355,9 @@ u32 glk_color_ctl(const struct intel_plane_state *plane_state)
> color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
> else
> color_ctl |= PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709;
> +
> + if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
> }
>
> return color_ctl;
> @@ -13830,7 +13836,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> drm_plane_create_color_properties(&primary->base,
> BIT(DRM_COLOR_YCBCR_BT601) |
> BIT(DRM_COLOR_YCBCR_BT709),
> - BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
> + BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
> + BIT(DRM_COLOR_YCBCR_FULL_RANGE),
> DRM_COLOR_YCBCR_BT709,
> DRM_COLOR_YCBCR_LIMITED_RANGE);
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index ba433bf40189..6276322fd8ad 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -387,7 +387,8 @@ vlv_update_clrc(const struct intel_plane_state *plane_state)
> enum plane_id plane_id = plane->id;
> int con, bri, sh_sin, sh_cos;
>
> - if (intel_format_is_yuv(fb->format->format)) {
> + if (intel_format_is_yuv(fb->format->format) &&
> + plane_state->base.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) {
> /*
> * expand limited range to full range.
> * contrast is applied first, then brightness
> @@ -599,6 +600,9 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
> if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> sprctl |= SPRITE_YUV_CSC_FORMAT_BT709;
>
> + if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE;
> +
> if (fb->modifier == I915_FORMAT_MOD_X_TILED)
> sprctl |= SPRITE_TILED;
>
> @@ -739,6 +743,9 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
> dvscntr |= DVS_YUV_CSC_FORMAT_BT709;
>
> + if (plane_state->base.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
> + dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE;
> +
> if (fb->modifier == I915_FORMAT_MOD_X_TILED)
> dvscntr |= DVS_TILED;
>
> @@ -1248,7 +1255,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> drm_plane_create_color_properties(&intel_plane->base,
> BIT(DRM_COLOR_YCBCR_BT601) |
> BIT(DRM_COLOR_YCBCR_BT709),
> - BIT(DRM_COLOR_YCBCR_LIMITED_RANGE),
> + BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
> + BIT(DRM_COLOR_YCBCR_FULL_RANGE),
> DRM_COLOR_YCBCR_BT709,
> DRM_COLOR_YCBCR_LIMITED_RANGE);
>
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