[Intel-gfx] [PATCH] drm/i915: Remove WaDisableKillLogic and GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC for KBL and GLK.

[Ville Syrjälä]

On Mon, Jun 19, 2017 at 10:23:41AM -0700, Rodrigo Vivi wrote:
> When reviewing commit 46c26662d2f ("drm/i915/cfl: Introduce Coffee Lake workarounds.")
> Mika pointed out that Spec tells those 2 workarounds were not needed.
> 
> So when double checking I confirmed that and also that by Spec
> they only apply to SKL and BXT.
> 
> v2: Instead of increase the if/else move the wa
>     to individual platform functions. (Ville).
>     Also remove from GLK since spec only mentions SKL and BXT.

The spec seems to be telling me that these shouldn't needed on any
platform. But there are scary comments in the code saying that they
have been kept to cure some hangs. Probably best to wair for Mika to be
back to review this one.

> 
> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 26 ++++++++++++++++----------
>  1 file changed, 16 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a4487c5..33c3a9d 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -831,11 +831,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  			  FLOW_CONTROL_ENABLE |
>  			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>  
> -	/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
> -	if (!IS_COFFEELAKE(dev_priv))
> -		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> -				  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> -
>  	/* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
>  	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
>  		WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> @@ -894,11 +889,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  HDC_FORCE_NON_COHERENT);
>  
> -	/* WaDisableHDCInvalidation:skl,bxt,kbl */
> -	if (!IS_COFFEELAKE(dev_priv))
> -		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> -			   BDW_DISABLE_HDC_INVALIDATION);
> -
>  	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
>  	if (IS_SKYLAKE(dev_priv) ||
>  	    IS_KABYLAKE(dev_priv) ||
> @@ -1007,6 +997,14 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
>  	if (ret)
>  		return ret;
>  
> +	/* Syncing dependencies between camera and graphics:skl */
> +	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> +			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> +
> +	/* WaDisableHDCInvalidation:skl */
> +	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> +		   BDW_DISABLE_HDC_INVALIDATION);
> +
>  	return skl_tune_iz_hashing(engine);
>  }
>  
> @@ -1076,6 +1074,14 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>  		WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
>  			   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
>  
> +	/* Syncing dependencies between camera and graphics:bxt */
> +	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> +			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> +
> +	/* WaDisableHDCInvalidation:bxt */
> +	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> +		   BDW_DISABLE_HDC_INVALIDATION);
> +
>  	return 0;
>  }
>  
> -- 
> 1.9.1

-- 
Ville Syrjälä
Intel OTC