[Intel-gfx] [PATCH 06/19] drm/i915: align 64K objects to 2M

[Chris Wilson]

Quoting Matthew Auld (2017-06-21 21:33:32)
> We can't mix 64K and 4K pte's in the same page-table, so for now we
> align 64K objects to 2M to avoid any potential mixing. This is
> potentially wasteful but in reality shouldn't be too bad since this only
> applies to the virtual address space of a 48b PPGTT.
> 
> Suggested-by: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_vma.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index cee1d00dc085..596269172cd2 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -495,7 +495,15 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags)
>                 if (end > (1ULL << 32) &&
>                     vma->page_sizes.sg > I915_GTT_PAGE_SIZE) {
>                         u64 page_alignment =
> -                               rounddown_pow_of_two(vma->page_sizes.sg);
> +                               rounddown_pow_of_two(vma->page_sizes.sg |
> +                                                    I915_GTT_PAGE_SIZE_2M);
> +
> +                       /* We can't mix 64K and 4K PTEs in the same page-table (2M
> +                        * block), and so to avoid the ugliness and complexity of
> +                        * coloring we opt for just aligning 64K objects to 2M.
> +                        */
> +                       if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K)
> +                               size = round_up(size, I915_GTT_PAGE_SIZE_2M);

Why separate the logically connected ops? i.e put the round_up after the
alignment = max()

>  
>                         alignment = max(alignment, page_alignment);
>                 }
> -- 
> 2.9.4
> 
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