[Intel-gfx] [PATCH 09/19] drm/i915: disable GTT cache for 2M/1G pages

[Chris Wilson]

Quoting Matthew Auld (2017-06-21 21:33:35)
> When SW enables the use of 2M/1G pages, it must disable the GTT cache.
> 
> v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
> 
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b5b7372fcddc..3939977dddb8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8307,10 +8307,10 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>         /*
>          * WaGttCachingOffByDefault:bdw
> -        * GTT cache may not work with big pages, so if those
> -        * are ever enabled GTT cache may need to be disabled.
> +        * The GTT cache must be disabled if the system is planning to use
> +        * 2M/1G pages.
>          */
> -       I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
> +       I915_WRITE(HSW_GTT_CACHE_EN, 0);

Worth doing HAS_PAGE_SIZES() ? 0 : GTT_CACHE_EN_ALL ?

>  
>         /* WaKVMNotificationOnConfigChange:bdw */
>         I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
> -- 
> 2.9.4
>