[Intel-gfx] [PATCH 10/17] drm/i915: Gen3 HWSTAM is actually 32 bits

[Chris Wilson]

Quoting ville.syrjala at linux.intel.com (2017-06-22 12:55:48)
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Bspec claims that HWSTAM is only 16 bits on gen3, but the other
> interrupts registers are 32 bits and there are 18 valid interrupt
> bits. Hence a 16 bit HWSTAM wouldn't be able to contain all the
> bits, so it seems the spec is incorrect about the size of the
> register. And indeed I can clear bits 16 and 17 just fine with
> a 32 bit write. So let's adjust the code to treat the register
> as 32 bits.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Acked-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris