[Intel-gfx] [PATCH 17/17] drm/i915: Rewrite GMCH irq handlers to follow the VLV/CHV pattern

[Chris Wilson]

Quoting ville.syrjala at linux.intel.com (2017-06-22 12:55:55)
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Eliminate the loops from the gen2-3 irq handlers by following the same
> trick used for VLV/CHV, ie. clear IER around acking the interrupts.
> That way if some IIR bits still remain set we'll get another edge (and
> thus another CPU interrupt) when the IER gets restored.
> 
> This shouldn't really be necessary when level triggered PCI interrupts
> are used (gen2, some gen3), but let's follow the same pattern in
> all the handlers so that we don't have to worry about MSI being enabled
> or not. And consistency should help avoid confusing the reader as well.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Having a common approach that just works is definitely worth it.
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

Interrupts aren't so much of a concern for me for pre-snb, but every
mmio read prior to waking up a waiter should be justified :) Before
ilk, we have to run the entire interrupt handler before userspace can
proceed. Just something to bear in mind, and prune as much as possible.
-Chris