[Intel-gfx] [PATCH v2] drm/i915: There is only one fault register from Gen8 onwards

[Michel Thierry]

Until Haswell/Baytrail, the hardware used to have a per engine fault
register (e.g. 0x4094 - render fault register, 0x4194 - media fault
register, etc). But since Broadwell, all these registers were combined
into a singe one, which specifies the engine id in bits 14:12.

Luckily, the additional register addresses haven't been reused, but we
should not been reading (and writing to) registers that do not exist.

v2: Rename fault variable, use INTEL_GEN (Chris).

References: IHD-OS-BDW-Vol 2c-11.15, page 75.
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Signed-off-by: Michel Thierry <michel.thierry at intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c   | 42 +++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/i915_gpu_error.c |  8 ++++---
 drivers/gpu/drm/i915/i915_reg.h       |  2 ++
 3 files changed, 37 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index de67084d5fcf..c840d4184a4f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1996,25 +1996,43 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
 {
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
+	u32 fault;
 
-	if (INTEL_INFO(dev_priv)->gen < 6)
+	if (INTEL_GEN(dev_priv) < 6)
 		return;
 
-	for_each_engine(engine, dev_priv, id) {
-		u32 fault_reg;
-		fault_reg = I915_READ(RING_FAULT_REG(engine));
-		if (fault_reg & RING_FAULT_VALID) {
+	/* From GEN8 onwards we only have one 'All Engine Fault Register' */
+	if (INTEL_GEN(dev_priv) >= 8) {
+		fault = I915_READ(GEN8_RING_FAULT_REG);
+		if (fault & RING_FAULT_VALID) {
 			DRM_DEBUG_DRIVER("Unexpected fault\n"
 					 "\tAddr: 0x%08lx\n"
-					 "\tAddress space: %s\n"
+					 "\tEngine ID: %d\n"
 					 "\tSource ID: %d\n"
 					 "\tType: %d\n",
-					 fault_reg & PAGE_MASK,
-					 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
-					 RING_FAULT_SRCID(fault_reg),
-					 RING_FAULT_FAULT_TYPE(fault_reg));
-			I915_WRITE(RING_FAULT_REG(engine),
-				   fault_reg & ~RING_FAULT_VALID);
+					 fault & PAGE_MASK,
+					 GEN8_RING_FAULT_ENGINE_ID(fault),
+					 RING_FAULT_SRCID(fault),
+					 RING_FAULT_FAULT_TYPE(fault));
+			I915_WRITE(GEN8_RING_FAULT_REG,
+				   fault & ~RING_FAULT_VALID);
+		}
+	} else {
+		for_each_engine(engine, dev_priv, id) {
+			fault = I915_READ(RING_FAULT_REG(engine));
+			if (fault & RING_FAULT_VALID) {
+				DRM_DEBUG_DRIVER("Unexpected fault\n"
+						 "\tAddr: 0x%08lx\n"
+						 "\tAddress space: %s\n"
+						 "\tSource ID: %d\n"
+						 "\tType: %d\n",
+						 fault & PAGE_MASK,
+						 fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
+						 RING_FAULT_SRCID(fault),
+						 RING_FAULT_FAULT_TYPE(fault));
+				I915_WRITE(RING_FAULT_REG(engine),
+					   fault & ~RING_FAULT_VALID);
+			}
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index ae70283470a6..b7f147b1b6dd 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1167,11 +1167,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 
 	if (INTEL_GEN(dev_priv) >= 6) {
 		ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
-		ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
-		if (INTEL_GEN(dev_priv) >= 8)
+		if (INTEL_GEN(dev_priv) >= 8) {
 			gen8_record_semaphore_state(error, engine, ee);
-		else
+			ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
+		} else {
 			gen6_record_semaphore_state(engine, ee);
+			ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
+		}
 	}
 
 	if (INTEL_GEN(dev_priv) >= 4) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c8647cfa81ba..54a828aad777 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2149,6 +2149,8 @@ enum skl_disp_power_wells {
 #define   ARB_MODE_SWIZZLE_BDW	(1<<1)
 #define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
 #define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100*(engine)->hw_id)
+#define GEN8_RING_FAULT_REG	_MMIO(0x4094)
+#define   GEN8_RING_FAULT_ENGINE_ID(x)	(((x) >> 12) & 0x7)
 #define   RING_FAULT_GTTSEL_MASK (1<<11)
 #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
 #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
-- 
2.11.0