[Intel-gfx] [PATCH 3/5] drm/i915% Store vma gtt offset in plane state
ville.syrjala at linux.intel.com
ville.syrjala at linux.intel.com
Thu Jun 29 13:49:46 UTC 2017
From: Ville Syrjälä <ville.syrjala at linux.intel.com>
To avoid having to deference plane_state->vma during the commit phase of
plane updates, let's store the vma gtt offset (or the bus address when
we need it) in the plane state. This is crucial for doing the modeset
operations during GPU reset as as plane_state->vma gets cleared when we
duplicate the state and we won't be calling .prepare_fb() during GPU
reset plane commits.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 38 +++++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_drv.h | 6 +-----
drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
3 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4e03ca6c946f..4ce81a694bd2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2744,7 +2744,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
if (!state->vma)
continue;
- if (intel_plane_ggtt_offset(state) == plane_config->base) {
+ if (state->gtt_offset == plane_config->base) {
fb = c->primary->fb;
drm_framebuffer_reference(fb);
goto valid_fb;
@@ -2771,6 +2771,8 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
mutex_lock(&dev->struct_mutex);
intel_state->vma =
intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
+ intel_state->gtt_offset = i915_ggtt_offset(intel_state->vma);
+
mutex_unlock(&dev->struct_mutex);
if (IS_ERR(intel_state->vma)) {
DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
@@ -3122,19 +3124,16 @@ static void i9xx_update_primary_plane(struct intel_plane *primary,
I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE_FW(DSPSURF(plane),
- intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ plane_state->gtt_offset + crtc->dspaddr_offset);
I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
} else if (INTEL_GEN(dev_priv) >= 4) {
I915_WRITE_FW(DSPSURF(plane),
- intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ plane_state->gtt_offset + crtc->dspaddr_offset);
I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
} else {
I915_WRITE_FW(DSPADDR(plane),
- intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ plane_state->gtt_offset + crtc->dspaddr_offset);
}
POSTING_READ_FW(reg);
@@ -3395,7 +3394,7 @@ static void skylake_update_primary_plane(struct intel_plane *plane,
}
I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_state->gtt_offset + surf_addr);
POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
@@ -9185,15 +9184,9 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
- const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
u32 base;
- if (INTEL_INFO(dev_priv)->cursor_needs_physical)
- base = obj->phys_handle->busaddr;
- else
- base = intel_plane_ggtt_offset(plane_state);
-
- base += plane_state->main.offset;
+ base = plane_state->gtt_offset + plane_state->main.offset;
/* ILK+ do this automagically */
if (HAS_GMCH_DISPLAY(dev_priv) &&
@@ -10846,8 +10839,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
work->old_vma = to_intel_plane_state(primary->state)->vma;
to_intel_plane_state(primary->state)->vma = vma;
+ to_intel_plane_state(primary->state)->gtt_offset =
+ i915_ggtt_offset(vma);
- work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
+ work->gtt_offset = to_intel_plane_state(primary->state)->gtt_offset +
+ intel_crtc->dspaddr_offset;
work->rotation = crtc->primary->state->rotation;
/*
@@ -10903,6 +10899,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
i915_add_request(request);
cleanup_unpin:
to_intel_plane_state(primary->state)->vma = work->old_vma;
+ to_intel_plane_state(primary->state)->gtt_offset =
+ i915_ggtt_offset(work->old_vma);
intel_unpin_fb_vma(vma);
cleanup_pending:
atomic_dec(&intel_crtc->unpin_work_count);
@@ -13344,6 +13342,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,
DRM_DEBUG_KMS("failed to attach phys object\n");
return ret;
}
+ to_intel_plane_state(new_state)->gtt_offset =
+ obj->phys_handle->busaddr;
} else {
struct i915_vma *vma;
@@ -13354,6 +13354,8 @@ intel_prepare_plane_fb(struct drm_plane *plane,
}
to_intel_plane_state(new_state)->vma = vma;
+ to_intel_plane_state(new_state)->gtt_offset =
+ i915_ggtt_offset(vma);
}
}
@@ -13657,6 +13659,8 @@ intel_legacy_cursor_update(struct drm_plane *plane,
DRM_DEBUG_KMS("failed to attach phys object\n");
goto out_unlock;
}
+ to_intel_plane_state(new_plane_state)->gtt_offset =
+ intel_fb_obj(fb)->phys_handle->busaddr;
} else {
struct i915_vma *vma;
@@ -13669,6 +13673,8 @@ intel_legacy_cursor_update(struct drm_plane *plane,
}
to_intel_plane_state(new_plane_state)->vma = vma;
+ to_intel_plane_state(new_plane_state)->gtt_offset =
+ i915_ggtt_offset(vma);
}
old_fb = old_plane_state->fb;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d17a32437f07..67efbc7de559 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -405,6 +405,7 @@ struct intel_plane_state {
struct drm_plane_state base;
struct drm_rect clip;
struct i915_vma *vma;
+ u32 gtt_offset; /* GGTT offset, or bus address */
struct {
u32 offset;
@@ -1482,11 +1483,6 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
-static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
-{
- return i915_ggtt_offset(state->vma);
-}
-
u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0c650c2cbca8..eced0772ed03 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -300,7 +300,7 @@ skl_update_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_state->gtt_offset + surf_addr);
POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -477,7 +477,7 @@ vlv_update_plane(struct intel_plane *plane,
I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
I915_WRITE_FW(SPSURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
+ plane_state->gtt_offset + sprsurf_offset);
POSTING_READ_FW(SPSURF(pipe, plane_id));
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -615,7 +615,7 @@ ivb_update_plane(struct intel_plane *plane,
I915_WRITE_FW(SPRSCALE(pipe), sprscale);
I915_WRITE_FW(SPRCTL(pipe), sprctl);
I915_WRITE_FW(SPRSURF(pipe),
- intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
+ plane_state->gtt_offset + sprsurf_offset);
POSTING_READ_FW(SPRSURF(pipe));
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -747,7 +747,7 @@ g4x_update_plane(struct intel_plane *plane,
I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
I915_WRITE_FW(DVSSURF(pipe),
- intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
+ plane_state->gtt_offset + dvssurf_offset);
POSTING_READ_FW(DVSSURF(pipe));
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
--
2.13.0
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