[Intel-gfx] [PATCH 2/3] drm/i915: Fix race between pipe update and vblank irq

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Make sure that we have an up to date vblank counter value for sending
out the completion event. On gen2/3 the vblank irq fires at frame start
rather than at start of vblank, so if we perform an update between
vblank start and frame start we would potentially sample a stale vblank
counter value, and thus send out the event one frame too soon.

Cc: Daniel Vetter <daniel at ffwll.ch>
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0c650c2cbca8..61681a11086a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -197,7 +197,7 @@ void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work
 	 * event outside of the critical section - the spinlock might spin for a
 	 * while ... */
 	if (crtc->base.state->event) {
-		WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
+		WARN_ON(drm_crtc_vblank_get_accurate(&crtc->base) != 0);
 
 		spin_lock(&crtc->base.dev->event_lock);
 		drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
-- 
2.13.0