[Intel-gfx] [PATCH v2 8/8] drm/i915: Remove duplicate DDI enabling logic from MST path

[Ville Syrjälä]

On Wed, Mar 01, 2017 at 04:13:18PM +0200, Ander Conselvan de Oliveira wrote:
> The logic to enable a DDI in intel_mst_pre_enable_dp() is essentially
> the same as in intel_ddi_pre_enable_dp(). So reuse the latter function
> by calling the post_disable hook on the intel_dig_port instead of
> duplicating that code.
> 
> v2: Don't oops because of a NULL encoder->crtc. (Ville)
> Cc: Imre Deak <imre.deak at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c    |  2 ++
>  drivers/gpu/drm/i915/intel_dp_mst.c | 23 +++--------------------
>  2 files changed, 5 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 2f26c75..208500a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1714,6 +1714,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>  	enum port port = intel_ddi_get_encoder_port(encoder);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
>  
> +	WARN_ON(link_mst && port == PORT_A);
> +

MST isn't allowed on port E either IIRC, so might want to warn for
that one as well.

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

>  	intel_dp_set_link_params(intel_dp, link_rate, lane_count,
>  				 link_mst);
>  	if (encoder->type == INTEL_OUTPUT_EDP)
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index a8334e1..094cbdc 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -159,26 +159,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
>  
>  	DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
>  
> -	if (intel_dp->active_mst_links == 0) {
> -		intel_ddi_clk_select(&intel_dig_port->base,
> -				     pipe_config->shared_dpll);
> -
> -		intel_display_power_get(dev_priv,
> -					intel_dig_port->ddi_io_power_domain);
> -
> -		intel_prepare_dp_ddi_buffers(&intel_dig_port->base);
> -		intel_dp_set_link_params(intel_dp,
> -					 pipe_config->port_clock,
> -					 pipe_config->lane_count,
> -					 true);
> -
> -		intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
> -
> -		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> -
> -		intel_dp_start_link_train(intel_dp);
> -		intel_dp_stop_link_train(intel_dp);
> -	}
> +	if (intel_dp->active_mst_links == 0)
> +		intel_dig_port->base.pre_enable(&intel_dig_port->base,
> +						pipe_config, NULL);
>  
>  	ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr,
>  				       connector->port,
> -- 
> 2.9.3

-- 
Ville Syrjälä
Intel OTC