[Intel-gfx] [PATCH] drm/i915: Extend residency counter ranges on chv and byt

[Chris Wilson]

On Thu, Mar 02, 2017 at 08:01:40PM +0200, Mika Kuoppala wrote:
> We were passively acting on the high counter value bit
> and as it was never set, we were only utilizing the
> the 32bits of resolution. As the divisor with these platforms
> is quite high, the wrap around happened in the less than 13 seconds.
> 
> If we toggle the resolution bit in the control register and
> read twice we can get 8 bits more, bringing the wrap in
> 54 minute range.
> 
> Reported-by: Len Brown <len.brown at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Len Brown <len.brown at intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_sysfs.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index af0ac9f..807d7be 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -53,17 +53,26 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
>  
>  	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> -		units = 1;
> +		u32 lower, upper;
>  		div = dev_priv->czclk_freq;
>  
> -		if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
> -			units <<= 8;
> +		I915_WRITE(VLV_COUNTER_CONTROL,
> +			   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> +		upper = I915_READ(reg);
> +
> +		I915_WRITE(VLV_COUNTER_CONTROL,
> +			   _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
> +		lower = I915_READ(reg);

u64 vlv_read_counter(struct drm_i915_private *dev_priv, i915_reg_t reg)
{
	u32 upper, lower, tmp, saved_ctl;
	unsigned int fw_domains;

	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg, FW_REG_READ);

	/* Lock out others from using VLV_COUNTER_CONTROL */
	spin_lock_irq(&dev_priv->uncore.lock);
	intel_uncore_forcewake_get__locked(dev_priv);

	saved_ctl =
		I915_READ_FW(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH;

	I915_WRITE_FW(VLV_COUNTER_CONTROL,
		      MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
	tmp = I915_READ_FW(reg);

	do {
		upper = tmp;

		I915_WRITE_FW(VLV_COUNTER_CONTROL,
			      _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
		lower = I915_READ(reg);

		I915_WRITE_FW(VLV_COUNTER_CONTROL,
			      MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
		tmp = I915_READ_FW(reg);
	} while (tmp != upper);

	I915_WRITE_FW(VLV_COUNTER_CONTROL,
		      VLV_COUNT_RANGE_HIGH << 16 | save_ctl);

	intel_uncore_forcewake_put__locked(dev_priv);
	spin_lock_irq(&dev_priv->uncore.lock);

	return (u64)upper << 8 | lower;
}

-- 
Chris Wilson, Intel Open Source Technology Centre