[Intel-gfx] [PATCH 04/15] drm/i915: add page_size_mask to dev_info
Mika Kuoppala
mika.kuoppala at linux.intel.com
Tue Mar 7 08:56:20 UTC 2017
Matthew Auld <matthew.auld at intel.com> writes:
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_gem_gtt.h | 14 ++++++++++++++
> drivers/gpu/drm/i915/i915_pci.c | 23 ++++++++++++++++++++++-
> 3 files changed, 37 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1fd4128a10b1..e45b8d74cebf 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -913,6 +913,7 @@ struct intel_device_info {
> enum intel_platform platform;
> u8 ring_mask; /* Rings supported by the HW */
> u8 num_rings;
> + unsigned long page_size_mask; /* page sizes supported by the HW */
> #define DEFINE_FLAG(name) u8 name:1
> DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
> #undef DEFINE_FLAG
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index fb15684c1d83..6c90a2ffd0e1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -43,8 +43,18 @@
> #include "i915_selftest.h"
>
> #define I915_GTT_PAGE_SIZE 4096UL
> +#define I915_GTT_PAGE_SIZE_64K 65536UL
> +#define I915_GTT_PAGE_SIZE_2M 2097152UL
> +#define I915_GTT_PAGE_SIZE_1G 1073741824UL
> +
> +#define I915_GTT_PAGE_SIZE_MASK (I915_GTT_PAGE_SIZE | \
> + I915_GTT_PAGE_SIZE_64K | \
> + I915_GTT_PAGE_SIZE_2M | \
> + I915_GTT_PAGE_SIZE_1G)
> +
> #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
>
> +
> #define I915_FENCE_REG_NONE -1
> #define I915_MAX_NUM_FENCES 32
> /* 32 fences + sign bit for FENCE_REG_NONE */
> @@ -143,6 +153,10 @@ typedef u64 gen8_ppgtt_pml4e_t;
> #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
> #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
>
> +#define GEN8_PDPE_PS_1G BIT(7)
> +#define GEN8_PDE_PS_2M BIT(7)
Just a minor bikeshed here to help the reader:
Show the PDE entries first and from smallest first,
then have one empty line before the PDPE entry. Also
this patch doesn't seem to be needing these so
consider moving these to the patch that does.
-Mika
> +#define GEN8_PDE_IPS_64K BIT(11)
> +
> struct sg_table;
>
> struct intel_rotation_info {
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 732101ed57fb..5abb7d84b65a 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -56,6 +56,10 @@
> .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
>
> /* Keep in gen based order, and chronological order within a gen */
> +
> +#define GEN_DEFAULT_PAGE_SZ \
> + .page_size_mask = I915_GTT_PAGE_SIZE
> +
> #define GEN2_FEATURES \
> .gen = 2, .num_pipes = 1, \
> .has_overlay = 1, .overlay_needs_physical = 1, \
> @@ -63,6 +67,7 @@
> .hws_needs_physical = 1, \
> .ring_mask = RENDER_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> + GEN_DEFAULT_PAGE_SZ, \
> CURSOR_OFFSETS
>
> static const struct intel_device_info intel_i830_info = {
> @@ -95,6 +100,7 @@ static const struct intel_device_info intel_i865g_info = {
> .has_gmch_display = 1, \
> .ring_mask = RENDER_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> + GEN_DEFAULT_PAGE_SZ, \
> CURSOR_OFFSETS
>
> static const struct intel_device_info intel_i915g_info = {
> @@ -153,6 +159,7 @@ static const struct intel_device_info intel_pineview_info = {
> .has_gmch_display = 1, \
> .ring_mask = RENDER_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> + GEN_DEFAULT_PAGE_SZ, \
> CURSOR_OFFSETS
>
> static const struct intel_device_info intel_i965g_info = {
> @@ -193,6 +200,7 @@ static const struct intel_device_info intel_gm45_info = {
> .has_gmbus_irq = 1, \
> .ring_mask = RENDER_RING | BSD_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> + GEN_DEFAULT_PAGE_SZ, \
> CURSOR_OFFSETS
>
> static const struct intel_device_info intel_ironlake_d_info = {
> @@ -218,6 +226,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
> .has_hw_contexts = 1, \
> .has_aliasing_ppgtt = 1, \
> GEN_DEFAULT_PIPEOFFSETS, \
> + GEN_DEFAULT_PAGE_SZ, \
> CURSOR_OFFSETS
>
> static const struct intel_device_info intel_sandybridge_d_info = {
> @@ -244,6 +253,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
> .has_aliasing_ppgtt = 1, \
> .has_full_ppgtt = 1, \
> GEN_DEFAULT_PIPEOFFSETS, \
> + GEN_DEFAULT_PAGE_SZ, \
> IVB_CURSOR_OFFSETS
>
> static const struct intel_device_info intel_ivybridge_d_info = {
> @@ -282,6 +292,7 @@ static const struct intel_device_info intel_valleyview_info = {
> .has_full_ppgtt = 1,
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> .display_mmio_offset = VLV_DISPLAY_BASE,
> + GEN_DEFAULT_PAGE_SZ,
> GEN_DEFAULT_PIPEOFFSETS,
> CURSOR_OFFSETS
> };
> @@ -308,7 +319,8 @@ static const struct intel_device_info intel_haswell_info = {
> BDW_COLORS, \
> .has_logical_ring_contexts = 1, \
> .has_full_48bit_ppgtt = 1, \
> - .has_64bit_reloc = 1
> + .has_64bit_reloc = 1, \
> + .page_size_mask = I915_GTT_PAGE_SIZE | I915_GTT_PAGE_SIZE_2M | I915_GTT_PAGE_SIZE_1G
>
> static const struct intel_device_info intel_broadwell_info = {
> BDW_FEATURES,
> @@ -341,13 +353,18 @@ static const struct intel_device_info intel_cherryview_info = {
> .has_aliasing_ppgtt = 1,
> .has_full_ppgtt = 1,
> .display_mmio_offset = VLV_DISPLAY_BASE,
> + .page_size_mask = I915_GTT_PAGE_SIZE | I915_GTT_PAGE_SIZE_64K | I915_GTT_PAGE_SIZE_2M | I915_GTT_PAGE_SIZE_1G,
> GEN_CHV_PIPEOFFSETS,
> CURSOR_OFFSETS,
> CHV_COLORS,
> };
>
> +#define GEN9_DEFAULT_PAGE_SZ \
> + .page_size_mask = I915_GTT_PAGE_SIZE | I915_GTT_PAGE_SIZE_64K | I915_GTT_PAGE_SIZE_2M | I915_GTT_PAGE_SIZE_1G
> +
> static const struct intel_device_info intel_skylake_info = {
> BDW_FEATURES,
> + GEN9_DEFAULT_PAGE_SZ,
> .platform = INTEL_SKYLAKE,
> .gen = 9,
> .has_csr = 1,
> @@ -357,6 +374,7 @@ static const struct intel_device_info intel_skylake_info = {
>
> static const struct intel_device_info intel_skylake_gt3_info = {
> BDW_FEATURES,
> + GEN9_DEFAULT_PAGE_SZ,
> .platform = INTEL_SKYLAKE,
> .gen = 9,
> .has_csr = 1,
> @@ -389,6 +407,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
> .has_aliasing_ppgtt = 1, \
> .has_full_ppgtt = 1, \
> .has_full_48bit_ppgtt = 1, \
> + GEN9_DEFAULT_PAGE_SZ, \
> GEN_DEFAULT_PIPEOFFSETS, \
> IVB_CURSOR_OFFSETS, \
> BDW_COLORS
> @@ -409,6 +428,7 @@ static const struct intel_device_info intel_geminilake_info = {
>
> static const struct intel_device_info intel_kabylake_info = {
> BDW_FEATURES,
> + GEN9_DEFAULT_PAGE_SZ,
> .platform = INTEL_KABYLAKE,
> .gen = 9,
> .has_csr = 1,
> @@ -418,6 +438,7 @@ static const struct intel_device_info intel_kabylake_info = {
>
> static const struct intel_device_info intel_kabylake_gt3_info = {
> BDW_FEATURES,
> + GEN9_DEFAULT_PAGE_SZ,
> .platform = INTEL_KABYLAKE,
> .gen = 9,
> .has_csr = 1,
> --
> 2.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
More information about the Intel-gfx
mailing list