[Intel-gfx] [PATCH v2] drm/i915/cmdparser: Limit clflush to active cachelines

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> We only need to clflush those cachelines that we have validated to be
> read by the GPU. Userspace typically fills the batch length in
> correctly, the exceptions tend to be explicit tests within igt.
>
> v2: Use ptr_mask_bits() to make Mika happy
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 21b1cd917d81..787980d52272 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -1330,8 +1330,10 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
>  		ret = -EINVAL;
>  	}
>  
> -	if (ret == 0 && needs_clflush_after)
> -		drm_clflush_virt_range(shadow_batch_obj->mm.mapping, batch_len);
> +	if (ret == 0 && needs_clflush_after) {
> +		void *ptr = ptr_mask_bits(shadow_batch_obj->mm.mapping);
> +		drm_clflush_virt_range(ptr, (void *)cmd - ptr);

Your ptr is page aligned, and the cmd is pointing to a BATCH_BUFFER_END
right at the next cacheline boundary. Apparently in this case you would
get flush only to the previous cacheline and not the one containg the
BB_END?

-Mika

> +	}
>  	i915_gem_object_unpin_map(shadow_batch_obj);
>  
>  	return ret;
> -- 
> 2.11.0