[Intel-gfx] [PATCH] drm/i915: Replace irq_seqno_barrier on hws write with a clflush

[Chris Wilson]

On Tue, Mar 14, 2017 at 11:38:59AM +0000, Chris Wilson wrote:
> When manually overwriting the HWS, rather than assume irq_seqno_barrier
> does the right thing, we can explicitly flush the cacheline instead.
> This avoids us calling the engine->irq_seqno_barrier() from an illegal
> context:

Drat, this was meant to be the other patch that I missent!
Sorry for the noise
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre