[Intel-gfx] [PATCH v2] drm/i915/glk: Enable pooled EUs for Geminilake

[Mika Kuoppala]

Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>
writes:

> Geminilake also supports pooled EUs. Enable it.
>
> It is unclear if the recommendation to disable it for 2x6 configurations
> from commit e015dd69b2cf ("drm/i915/bxt: Add WaEnablePooledEuFor2x6")
> should also apply to GLK, but it is applied anyway to be on the safe
> side. That restriction can be lifted later if determined not to impact
> performance.
>
> The extra restriction should not impact user space either. The only user
> space that uses this feature is Beignet, and it only does so for 3x6
> devices. See See Beignet's commit 6901899ec90a ("Runtime: set the sub
> slice according to kernel pooled EU configure.").
>
> v2: Improve commit message. (Mika, Roy)
>
> Cc: Arun Siluvery <arun.siluvery at intel.com>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Cc: Yang Rong <rong.r.yang at intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_device_info.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 9fc6ab7..7d01dfe 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -197,8 +197,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  		IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1;
>  	sseu->has_eu_pg = sseu->eu_per_subslice > 2;
>  
> -	if (IS_BROXTON(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv)) {
>  #define IS_SS_DISABLED(ss)	(!(sseu->subslice_mask & BIT(ss)))
> +		info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3;
> +
>  		/*
>  		 * There is a HW issue in 2x6 fused down parts that requires
>  		 * Pooled EU to be enabled as a WA. The pool configuration
> @@ -206,9 +208,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
>  		 * doesn't affect if the device has all 3 subslices enabled.
>  		 */
>  		/* WaEnablePooledEuFor2x6:bxt */
> -		info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) ||
> -				       (hweight8(sseu->subslice_mask) == 2 &&
> -					INTEL_REVID(dev_priv) < BXT_REVID_C0));
> +		info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 &&
> +					IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST));
>  
>  		sseu->min_eu_in_pool = 0;
>  		if (info->has_pooled_eu) {
> -- 
> 2.9.3
>
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