[Intel-gfx] [PATCH] drm/i915: Skip force-wake for uncached mmio flush of GGTT writes

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> The trick of using an uncached mmio read to ensure that the GGTT writes
> are flushed does not require us to do the forcewake dance, so avoid it
> in the hope of reducing the frequency that we do keep the device forced
> awake.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 5e280e3bfd86..d468300e2f05 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3094,8 +3094,11 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
>  	 * system agents we cannot reproduce this behaviour).
>  	 */
>  	wmb();
> -	if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
> -		POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
> +	if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
> +		spin_lock_irq(&dev_priv->uncore.lock);
> +		POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
> +		spin_unlock_irq(&dev_priv->uncore.lock);
> +	}
>

Why is it so that the flushing (from gpu side) doesn't need
the rc6?

Also noticed that write domain check, prior to calling this,
in set_to_cpu_domain() is redundant.

-Mika

>  	intel_fb_obj_flush(obj, write_origin(obj, I915_GEM_DOMAIN_GTT));
>  
> -- 
> 2.11.0
>
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