[Intel-gfx] [PATCH v7 08/21] drm/i915/slpc: Add SLPC communication interfaces
Sagar Arun Kamble
sagar.a.kamble at intel.com
Wed Mar 22 10:03:41 UTC 2017
Communication with SLPC is via Host to GuC interrupt through
shared data and parameters. This patch defines the structure of
shared data, parameters, data structure to be passed as input and
received as output from SLPC. This patch also defines the events
to be sent as input and status values output by GuC on processing
SLPC events. SLPC shared data has details of SKU type, Slice count,
IA Perf MSR values, SLPC state, Power source/plan, SLPC tasks status.
Parameters allow overriding task control, frequency range etc.
v1: fix whitespace (Sagar)
v2-v3: Rebase.
v4: Updated with GuC firmware v9.
v5: Added definition of input and output data structures for SLPC
events. Updated commit message.
v6: Removed definition of host2guc_slpc. Will be added in the next
patch that uses it. Commit subject update. Rebase.
v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent
throgh SLPC reset in case of engine reset. Moved all Host/SLPC
interfaces from later patches to this patch. Commit message update.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
drivers/gpu/drm/i915/intel_slpc.c | 39 +++++++
drivers/gpu/drm/i915/intel_slpc.h | 207 ++++++++++++++++++++++++++++++++++++++
2 files changed, 246 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 192e777..f1fe386 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -25,6 +25,45 @@
#include "i915_drv.h"
#include "intel_uc.h"
+struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
+ {SLPC_PARAM_TASK_ENABLE_GTPERF, "Enable task GTPERF"},
+ {SLPC_PARAM_TASK_DISABLE_GTPERF, "Disable task GTPERF"},
+ {SLPC_PARAM_TASK_ENABLE_BALANCER, "Enable task BALANCER"},
+ {SLPC_PARAM_TASK_DISABLE_BALANCER, "Disable task BALANCER"},
+ {SLPC_PARAM_TASK_ENABLE_DCC, "Enable task DCC"},
+ {SLPC_PARAM_TASK_DISABLE_DCC, "Disable task DCC"},
+ {SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ "Minimum GT frequency request for unslice"},
+ {SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ "Maximum GT frequency request for unslice"},
+ {SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ "Minimum GT frequency request for slice"},
+ {SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ "Maximum GT frequency request for slice"},
+ {SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+ "If non-zero, algorithm will slow down "
+ "frame-based applications to this frame-rate"},
+ {SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT,
+ "Lock GT frequency request to RPe"},
+ {SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+ "Set to TRUE to enable slowing framerate"},
+ {SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE,
+ "Prevent from changing the RC mode"},
+ {SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ,
+ "Override fused value of unslice RP0"},
+ {SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ,
+ "Override fused value of slice RP0"},
+ {SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+ "TRUE means enable Intelligent Bias Control"},
+ {SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+ "TRUE = enable eval mode when transitioning "
+ "from idle to active."},
+ {SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+ "FALSE = disable eval mode completely"},
+ {SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+ "Enable IBC when non-Gaming Mode is enabled"}
+};
+
void intel_slpc_init(struct drm_i915_private *dev_priv)
{
}
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index b135a30..31a029f 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -28,6 +28,213 @@ struct intel_slpc {
bool active;
};
+enum slpc_status {
+ SLPC_STATUS_OK = 0,
+ SLPC_STATUS_ERROR = 1,
+ SLPC_STATUS_ILLEGAL_COMMAND = 2,
+ SLPC_STATUS_INVALID_ARGS = 3,
+ SLPC_STATUS_INVALID_PARAMS = 4,
+ SLPC_STATUS_INVALID_DATA = 5,
+ SLPC_STATUS_OUT_OF_RANGE = 6,
+ SLPC_STATUS_NOT_SUPPORTED = 7,
+ SLPC_STATUS_NOT_IMPLEMENTED = 8,
+ SLPC_STATUS_NO_DATA = 9,
+ SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+ SLPC_STATUS_REGISTER_LOCKED = 11,
+ SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+ SLPC_STATUS_VALUE_ALREADY_SET = 13,
+ SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+ SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+ SLPC_STATUS_MEMIO_ERROR = 16,
+ SLPC_STATUS_EVENT_QUEUED_REQ_DPC = 17,
+ SLPC_STATUS_EVENT_QUEUED_NOREQ_DPC = 18,
+ SLPC_STATUS_NO_EVENT_QUEUED = 19,
+ SLPC_STATUS_OUT_OF_SPACE = 20,
+ SLPC_STATUS_TIMEOUT = 21,
+ SLPC_STATUS_NO_LOCK = 22,
+};
+
+enum slpc_event_id {
+ SLPC_EVENT_RESET = 0,
+ SLPC_EVENT_SHUTDOWN = 1,
+ SLPC_EVENT_PLATFORM_INFO_CHANGE = 2,
+ SLPC_EVENT_DISPLAY_MODE_CHANGE = 3,
+ SLPC_EVENT_FLIP_COMPLETE = 4,
+ SLPC_EVENT_QUERY_TASK_STATE = 5,
+ SLPC_EVENT_PARAMETER_SET = 6,
+ SLPC_EVENT_PARAMETER_UNSET = 7,
+};
+
+enum slpc_param_id {
+ SLPC_PARAM_TASK_ENABLE_GTPERF = 0,
+ SLPC_PARAM_TASK_DISABLE_GTPERF = 1,
+ SLPC_PARAM_TASK_ENABLE_BALANCER = 2,
+ SLPC_PARAM_TASK_DISABLE_BALANCER = 3,
+ SLPC_PARAM_TASK_ENABLE_DCC = 4,
+ SLPC_PARAM_TASK_DISABLE_DCC = 5,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ = 6,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ = 7,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ = 8,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ = 9,
+ SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS = 10,
+ SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT = 11,
+ SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING = 12,
+ SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE = 13,
+ SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ = 14,
+ SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ = 15,
+ SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING = 16,
+ SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO = 17,
+ SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE = 18,
+ SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE = 19,
+ SLPC_MAX_PARAM,
+ SLPC_KMD_MAX_PARAM = 32,
+};
+
+enum slpc_platform_sku {
+ SLPC_PLATFORM_SKU_UNDEFINED = 0,
+ SLPC_PLATFORM_SKU_ULX = 1,
+ SLPC_PLATFORM_SKU_ULT = 2,
+ SLPC_PLATFORM_SKU_T = 3,
+ SLPC_PLATFORM_SKU_MOBL = 4,
+ SLPC_PLATFORM_SKU_DT = 5,
+ SLPC_PLATFORM_SKU_UNKNOWN = 6,
+};
+
+enum slpc_power_source {
+ SLPC_POWER_SOURCE_UNDEFINED = 0,
+ SLPC_POWER_SOURCE_AC = 1,
+ SLPC_POWER_SOURCE_DC = 2,
+ SLPC_POWER_SOURCE_UNKNOWN = 3,
+};
+
+enum slpc_power_plan {
+ SLPC_POWER_PLAN_UNDEFINED = 0,
+ SLPC_POWER_PLAN_BATTERY_SAVER = 1,
+ SLPC_POWER_PLAN_BALANCED = 2,
+ SLPC_POWER_PLAN_PERFORMANCE = 3,
+ SLPC_POWER_PLAN_UNKNOWN = 4,
+};
+
+struct slpc_platform_info {
+ u8 platform_sku;
+ u8 slice_count;
+ u8 reserved;
+ u8 power_plan_source;
+ u8 P0_freq;
+ u8 P1_freq;
+ u8 Pe_freq;
+ u8 Pn_freq;
+ u32 reserved1;
+ u32 reserved2;
+} __packed;
+
+enum slpc_global_state {
+ SLPC_GLOBAL_STATE_NOT_RUNNING = 0,
+ SLPC_GLOBAL_STATE_INITIALIZING = 1,
+ SLPC_GLOBAL_STATE_RESETTING = 2,
+ SLPC_GLOBAL_STATE_RUNNING = 3,
+ SLPC_GLOBAL_STATE_SHUTTING_DOWN = 4,
+ SLPC_GLOBAL_STATE_ERROR = 5
+};
+
+struct slpc_task_state_data {
+ union {
+ u32 bitfield1;
+ struct {
+ u32 gtperf_task_active:1;
+ u32 gtperf_stall_possible:1;
+ u32 gtperf_gaming_mode:1;
+ u32 gtperf_target_fps:8;
+ u32 dcc_task_active:1;
+ u32 in_dcc:1;
+ u32 in_dct:1;
+ u32 freq_switch_active:1;
+ u32 ibc_enabled:1;
+ u32 ibc_active:1;
+ u32 pg1_enabled:1;
+ u32 pg1_active:1;
+ u32 reserved:13;
+ };
+ };
+ union {
+ u32 bitfield2;
+ struct {
+ u32 max_unslice_freq:8;
+ u32 min_unslice_freq:8;
+ u32 max_slice_freq:8;
+ u32 min_slice_freq:8;
+ };
+ };
+} __packed;
+
+#define SLPC_MAX_OVERRIDE_PARAMETERS 192
+#define SLPC_OVERRIDE_BITFIELD_SIZE ((SLPC_MAX_OVERRIDE_PARAMETERS + 31) / 32)
+
+struct slpc_shared_data {
+ u32 reserved;
+ u32 shared_data_size;
+ u32 global_state;
+ struct slpc_platform_info platform_info;
+ struct slpc_task_state_data task_state_data;
+ u32 override_parameters_set_bits[SLPC_OVERRIDE_BITFIELD_SIZE];
+ u32 override_parameters_values[SLPC_MAX_OVERRIDE_PARAMETERS];
+} __packed;
+
+enum slpc_reset_flags {
+ SLPC_RESET_FLAG_TDR_OCCURRED
+};
+
+#define SLPC_EVENT_MAX_INPUT_ARGS 7
+#define SLPC_EVENT_MAX_OUTPUT_ARGS 1
+
+union slpc_event_input_header {
+ u32 value;
+ struct {
+ u32 num_args:8;
+ u32 event_id:8;
+ };
+};
+
+struct slpc_event_input {
+ u32 h2g_action_id;
+ union slpc_event_input_header header;
+ u32 args[SLPC_EVENT_MAX_INPUT_ARGS];
+} __packed;
+
+union slpc_event_output_header {
+ u32 value;
+ struct {
+ u32 num_args:8;
+ u32 event_id:8;
+ u32 status:16;
+ };
+};
+
+struct slpc_event_output {
+ u32 reserved;
+ union slpc_event_output_header header;
+ u32 args[SLPC_EVENT_MAX_OUTPUT_ARGS];
+} __packed;
+
+#define SLPC_EVENT(id, argc) ((u32) (id) << 8 | (argc))
+#define SLPC_POWER_PLAN_SOURCE(plan, source) ((plan) | ((source) << 6))
+#define SLPC_POWER_PLAN(plan_source) ((plan_source) & 0x3F)
+#define SLPC_POWER_SOURCE(plan_source) ((plan_source) >> 6)
+
+/* Structures for exposing parameter details to user. */
+#define MAX_PARAM_DESCRIPTION_SIZE 160
+struct slpc_param {
+ enum slpc_param_id id;
+ char description[MAX_PARAM_DESCRIPTION_SIZE];
+};
+
+extern struct slpc_param slpc_paramlist[];
+
+#define SLPC_PARAM_TASK_DEFAULT 0
+#define SLPC_PARAM_TASK_ENABLED 1
+#define SLPC_PARAM_TASK_DISABLED 2
+#define SLPC_PARAM_TASK_UNKNOWN 3
+
/* intel_slpc.c */
void intel_slpc_init(struct drm_i915_private *dev_priv);
void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
--
1.9.1
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