[Intel-gfx] [PATCH v7 13/21] drm/i915/slpc: Add support for min/max frequency control

Sagar Arun Kamble sagar.a.kamble at intel.com
Wed Mar 22 10:03:46 UTC 2017


Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
    Replace HAS_SLPC with intel_slpc_active() (Paulo)

v2-v4: Rebase.

v5: Removed typecasting the frequency values to u32. (Chris)
    Changed intel_slpc_active to guc.slpc.enabled. Carved out
    SLPC helpers to set min and max frequencies.

v6: Rebase. Doing explicit SLPC reset on setting frequency to start sane
    and covered with RPM get/put. Caching SLPC limits post enabling first.

Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 46 ++++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/i915_sysfs.c   | 36 ++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_slpc.c   | 55 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h   |  5 ++++
 4 files changed, 132 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index cf8bd98..4af0b72 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4316,7 +4316,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	if (INTEL_GEN(dev_priv) < 6)
 		return -ENODEV;
 
-	*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
+	if (dev_priv->guc.slpc.active)
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->guc.slpc.max_unslice_freq);
+	else
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->rps.max_freq_softlimit);
 	return 0;
 }
 
@@ -4332,20 +4337,32 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 
 	DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
 
+	intel_runtime_pm_get(dev_priv);
+
 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
-	if (ret)
+	if (ret) {
+		intel_runtime_pm_put(dev_priv);
 		return ret;
+	}
 
 	/*
 	 * Turbo will still be enabled, but won't go above the set value.
 	 */
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_max_freq_set(dev_priv, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret;
+	}
+
 	hw_max = dev_priv->rps.max_freq;
 	hw_min = dev_priv->rps.min_freq;
 
 	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
 		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
 		return -EINVAL;
 	}
 
@@ -4356,6 +4373,8 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
+	intel_runtime_pm_put(dev_priv);
+
 	return 0;
 }
 
@@ -4371,7 +4390,12 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 	if (INTEL_GEN(dev_priv) < 6)
 		return -ENODEV;
 
-	*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
+	if (dev_priv->guc.slpc.active)
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->guc.slpc.min_unslice_freq);
+	else
+		*val = intel_gpu_freq(dev_priv,
+				      dev_priv->rps.min_freq_softlimit);
 	return 0;
 }
 
@@ -4387,21 +4411,33 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 
 	DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
 
+	intel_runtime_pm_get(dev_priv);
+
 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
-	if (ret)
+	if (ret) {
+		intel_runtime_pm_put(dev_priv);
 		return ret;
+	}
 
 	/*
 	 * Turbo will still be enabled, but won't go below the set value.
 	 */
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_min_freq_set(dev_priv, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret;
+	}
+
 	hw_max = dev_priv->rps.max_freq;
 	hw_min = dev_priv->rps.min_freq;
 
 	if (val < hw_min ||
 	    val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
 		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
 		return -EINVAL;
 	}
 
@@ -4412,6 +4448,8 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
 
 	mutex_unlock(&dev_priv->rps.hw_lock);
 
+	intel_runtime_pm_put(dev_priv);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index f3fdfda..c40b539e 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -327,9 +327,14 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			intel_gpu_freq(dev_priv,
-				       dev_priv->rps.max_freq_softlimit));
+	if (dev_priv->guc.slpc.active)
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.max_unslice_freq));
+	else
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->rps.max_freq_softlimit));
 }
 
 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
@@ -350,6 +355,13 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_max_freq_set(dev_priv, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret ? ret : count;
+	}
+
 	if (val < dev_priv->rps.min_freq ||
 	    val > dev_priv->rps.max_freq ||
 	    val < dev_priv->rps.min_freq_softlimit) {
@@ -384,9 +396,14 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
 {
 	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 
-	return snprintf(buf, PAGE_SIZE, "%d\n",
-			intel_gpu_freq(dev_priv,
-				       dev_priv->rps.min_freq_softlimit));
+	if (dev_priv->guc.slpc.active)
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->guc.slpc.min_unslice_freq));
+	else
+		return snprintf(buf, PAGE_SIZE, "%d\n",
+				intel_gpu_freq(dev_priv,
+					dev_priv->rps.min_freq_softlimit));
 }
 
 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
@@ -407,6 +424,13 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 
 	val = intel_freq_opcode(dev_priv, val);
 
+	if (dev_priv->guc.slpc.active) {
+		ret = intel_slpc_min_freq_set(dev_priv, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+		intel_runtime_pm_put(dev_priv);
+		return ret ? ret : count;
+	}
+
 	if (val < dev_priv->rps.min_freq ||
 	    val > dev_priv->rps.max_freq ||
 	    val > dev_priv->rps.max_freq_softlimit) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index 98b6f1f..f9d6d69 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -467,6 +467,7 @@ const char *intel_slpc_get_state_str(enum slpc_global_state state)
 	else
 		return "unknown";
 }
+
 bool intel_slpc_get_status(struct drm_i915_private *dev_priv)
 {
 	struct slpc_shared_data data;
@@ -479,6 +480,12 @@ bool intel_slpc_get_status(struct drm_i915_private *dev_priv)
 	switch (data.global_state) {
 	case SLPC_GLOBAL_STATE_RUNNING:
 		/* Capture required state from SLPC here */
+		dev_priv->guc.slpc.max_unslice_freq =
+				data.task_state_data.max_unslice_freq *
+				GEN9_FREQ_SCALER;
+		dev_priv->guc.slpc.min_unslice_freq =
+				data.task_state_data.min_unslice_freq *
+				GEN9_FREQ_SCALER;
 		ret = true;
 		break;
 	case SLPC_GLOBAL_STATE_ERROR:
@@ -515,6 +522,54 @@ static void intel_slpc_restore_default_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RP_CONTROL, dev_priv->guc.slpc.rp_control);
 }
 
+/*
+ * TODO: Add separate interfaces to set Max/Min Slice frequency.
+ * Since currently both slice and unslice are configured to same
+ * frequencies these unified interface relying on Unslice frequencies
+ * should be sufficient. These functions take frequency opcode as input.
+ */
+int intel_slpc_max_freq_set(struct drm_i915_private *dev_priv, u32 val)
+{
+	if (val < dev_priv->rps.min_freq ||
+	    val > dev_priv->rps.max_freq ||
+	    val < dev_priv->guc.slpc.min_unslice_freq)
+		return -EINVAL;
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+
+	intel_slpc_enable(dev_priv);
+
+	dev_priv->guc.slpc.max_unslice_freq = val;
+
+	return 0;
+}
+
+int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val)
+{
+	if (val < dev_priv->rps.min_freq ||
+	    val > dev_priv->rps.max_freq ||
+	    val > dev_priv->guc.slpc.max_unslice_freq)
+		return -EINVAL;
+
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+	intel_slpc_set_param(dev_priv,
+			     SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+			     intel_gpu_freq(dev_priv, val));
+
+	intel_slpc_enable(dev_priv);
+
+	dev_priv->guc.slpc.min_unslice_freq = val;
+
+	return 0;
+}
+
 void intel_slpc_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_guc *guc = &dev_priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 4b9de3f..5531523 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -29,6 +29,9 @@ struct intel_slpc {
 	struct i915_vma *vma;
 
 	u32 rp_control;
+	/* i915 cached SLPC frequency limits */
+	u32 min_unslice_freq;
+	u32 max_unslice_freq;
 };
 
 enum slpc_status {
@@ -252,6 +255,8 @@ void intel_slpc_read_shared_data(struct drm_i915_private *dev_priv,
 const char *intel_slpc_get_state_str(enum slpc_global_state state);
 bool intel_slpc_get_status(struct drm_i915_private *dev_priv);
 void intel_slpc_save_default_rps(struct drm_i915_private *dev_priv);
+int intel_slpc_max_freq_set(struct drm_i915_private *dev_priv, u32 val);
+int intel_slpc_min_freq_set(struct drm_i915_private *dev_priv, u32 val);
 void intel_slpc_init(struct drm_i915_private *dev_priv);
 void intel_slpc_cleanup(struct drm_i915_private *dev_priv);
 void intel_slpc_enable(struct drm_i915_private *dev_priv);
-- 
1.9.1



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