[Intel-gfx] [PATCH 2/6] drm/i915: Nuke ironlake_plane_ctl()

[Chris Wilson]

On Thu, Mar 23, 2017 at 09:27:08PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Share the code to compute the primary plane control register value
> between the i9xx and ilk codepaths as the differences are minimal.
> Actually there are no differences between g4x and ilk, so the
> current split doesn't really make any sense.
> 
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 58 ++++--------------------------------
>  1 file changed, 6 insertions(+), 52 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index aa2c85b2bf78..4f57ce982a72 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2974,9 +2974,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>  
>  	dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
>  
> -	if (IS_G4X(dev_priv))
> +	if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
> +	    IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
>  		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

Fortunately I remembered the explanation last time about vlv and chv,
and yes this does make that much more obvious.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre