[Intel-gfx] [PATCH v2] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters
clinton.a.taylor at intel.com
clinton.a.taylor at intel.com
Thu Mar 23 23:38:58 UTC 2017
From: Clint Taylor <clinton.a.taylor at intel.com>
Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane
signal if the Data Link N is greater than 0x80000.
Patch detects when 1 lane 5.4 GHz signal is being used and makes the maximum
value 20 bit instead of the maximum specification supported 24 bit value.
v2: Detect specific device that exhibits the issue.
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
Cc: Jani Nikula <jani.nikula at intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93578
Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++------
drivers/gpu/drm/i915/intel_dp.c | 14 ++++++++++++--
drivers/gpu/drm/i915/intel_dp_mst.c | 3 ++-
5 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5947a4..6869df9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -580,7 +580,8 @@ struct intel_link_m_n {
void intel_link_compute_m_n(int bpp, int nlanes,
int pixel_clock, int link_clock,
- struct intel_link_m_n *m_n);
+ struct intel_link_m_n *m_n,
+ bool reduced_n);
/* Interface history:
*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04c8f69..838d8d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4869,6 +4869,8 @@ enum {
#define DATA_LINK_M_N_MASK (0xffffff)
#define DATA_LINK_N_MAX (0x800000)
+/* Maximum N value useable on some DP->HDMI converters */
+#define DATA_LINK_REDUCED_N_MAX (0x80000)
#define _PIPEA_DATA_N_G4X 0x70054
#define _PIPEB_DATA_N_G4X 0x71054
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 010e5dd..143c7ac 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6139,7 +6139,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
- link_bw, &pipe_config->fdi_m_n);
+ link_bw, &pipe_config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
@@ -6315,9 +6315,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
}
static void compute_m_n(unsigned int m, unsigned int n,
- uint32_t *ret_m, uint32_t *ret_n)
+ uint32_t *ret_m, uint32_t *ret_n,
+ uint32_t max_link_n)
{
- *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
+ *ret_n = min_t(unsigned int, roundup_pow_of_two(n), max_link_n);
*ret_m = div_u64((uint64_t) m * *ret_n, n);
intel_reduce_m_n_ratio(ret_m, ret_n);
}
@@ -6325,16 +6326,23 @@ static void compute_m_n(unsigned int m, unsigned int n,
void
intel_link_compute_m_n(int bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
- struct intel_link_m_n *m_n)
+ struct intel_link_m_n *m_n,
+ bool reduced_n)
{
+ uint32_t max_link_n = DATA_LINK_N_MAX;
m_n->tu = 64;
+ if ((reduced_n) && (nlanes == 1) && (link_clock >= 540000))
+ max_link_n = DATA_LINK_REDUCED_N_MAX;
+
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
- &m_n->gmch_m, &m_n->gmch_n);
+ &m_n->gmch_m, &m_n->gmch_n,
+ max_link_n);
compute_m_n(pixel_clock, link_clock,
- &m_n->link_m, &m_n->link_n);
+ &m_n->link_m, &m_n->link_n,
+ max_link_n);
}
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fd96a6c..9c96f5f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1624,6 +1624,8 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
int common_rates[DP_MAX_SUPPORTED_RATES] = {};
int common_len;
uint8_t link_bw, rate_select;
+ char id[6];
+ bool reduced_n = false;
common_len = intel_dp_common_rates(intel_dp, common_rates);
@@ -1750,10 +1752,17 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
DRM_DEBUG_KMS("DP link bw required %i available %i\n",
mode_rate, link_avail);
+ /* Quirk to detect DP->HDMI converter */
+ drm_dp_downstream_id(&intel_dp->aux, id);
+ if (!strncmp(id , "7737" ,4)) {
+ reduced_n = true;
+ }
+
intel_link_compute_m_n(bpp, lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
- &pipe_config->dp_m_n);
+ &pipe_config->dp_m_n,
+ reduced_n);
if (intel_connector->panel.downclock_mode != NULL &&
dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
@@ -1761,7 +1770,8 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
intel_link_compute_m_n(bpp, lane_count,
intel_connector->panel.downclock_mode->clock,
pipe_config->port_clock,
- &pipe_config->dp_m2_n2);
+ &pipe_config->dp_m2_n2,
+ reduced_n);
}
/*
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 094cbdc..3303767 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -75,7 +75,8 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_link_compute_m_n(bpp, lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
- &pipe_config->dp_m_n);
+ &pipe_config->dp_m_n,
+ false);
pipe_config->dp_m_n.tu = slots;
--
1.7.9.5
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