[Intel-gfx] [PATCH 1/2] drm/i915: Sanitize display INIT power domain enabling

[Imre Deak]

On Fri, Mar 24, 2017 at 02:36:54PM +0200, Imre Deak wrote:
> For consistency move the INIT power domain enabling to happen at the
> same call-stack level everywhere. So far we didn't do this enabling
> during:
> - on GEN9 big-core when resuming from system freeze
> - on VLV on the i915_drm_suspend_late() error path
> 
> Fortunately neither of these depended on display power wells being
> enabled until proper references are taken by the modeset code. (This
> also means the we can probably remove the INIT power domain get/put
> from these places as a follow-up, after some more auditing.)
> 
> The current unpaired enable/disable was noticed by Ville during some
> earlier review.
> 
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c         | 6 ++++++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 2 --
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 6d9944a..6b10e37 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -592,6 +592,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
>  	intel_update_rawclk(dev_priv);
>  
>  	intel_power_domains_init_hw(dev_priv, false);
> +	/* Enable the INIT power domain wells for HW initialization. */
> +	intel_display_set_init_power(dev_priv, true);

Arr, this will result in HPD IRQs inited too early on VLV. Need to
rethink this.

>  
>  	intel_csr_ucode_init(dev_priv);
>  
> @@ -1559,6 +1561,8 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
>  		if (!fw_csr)
>  			intel_power_domains_init_hw(dev_priv, true);
>  
> +		intel_display_set_init_power(dev_priv, true);
> +
>  		goto out;
>  	}
>  
> @@ -1768,6 +1772,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
>  	if (IS_GEN9_LP(dev_priv) ||
>  	    !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
>  		intel_power_domains_init_hw(dev_priv, true);
> +	/* Enable the INIT power domain wells for HW initialization. */
> +	intel_display_set_init_power(dev_priv, true);
>  
>  	i915_gem_sanitize(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 012bc35..ecc43c6 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2715,8 +2715,6 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>  		mutex_unlock(&power_domains->lock);
>  	}
>  
> -	/* For now, we need the power well to be always enabled. */
> -	intel_display_set_init_power(dev_priv, true);
>  	/* Disable power support if the user asked so. */
>  	if (!i915.disable_power_well)
>  		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> -- 
> 2.5.0
> 
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