[Intel-gfx] [PATCH] drm/i915: Limit number of reads to stabilize rc6 counter reads

[Chris Wilson]

On Mon, Mar 27, 2017 at 01:07:58PM +0300, Mika Kuoppala wrote:
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> 
> > We have only 8bits of precise timestamps in which to complete our
> > upper/load reads, along with the switch between precision. This is not
> > always enough time to read the upper counter twice within the same time
> > slice, leading to hard lockups. Limit the number of times to prevent
> > an inifite loop (my fault for assuming we would have no trouble doing
> > the write + reads fast enough).
> >
> 
> We get here only with kasan enabled? Or even without?

It quite possibly is just a kasan artefact. Though we are chasing severe
latencies (>400us) due to mmio reads elsewhere (skl gt4e).
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre