[Intel-gfx] [PATCH v3 00/14] drm/i915/dp: link rate and lane count refactoring

[Jani Nikula]

v3 of [1], rebased and review addressed.

This might still conflict with some of Manasi's pending work, but I
think for the most parts we could start pushing these. The scales are
tipping, it'll be easier to rebase Manasi's stuff than this. Indeed some
of it may be easier to understand after the changes here.

BR,
Jani.


[1] http://mid.mail-archive.com/cover.1486131408.git.jani.nikula@intel.com


Jani Nikula (14):
  drm/i915/dp: use known correct array size in rate_to_index
  drm/i915/dp: return errors from rate_to_index()
  drm/i915/dp: rename rate_to_index() to intel_dp_rate_index() and reuse
  drm/i915/dp: cache source rates at init
  drm/i915/dp: generate and cache sink rate array for all DP, not just
    eDP 1.4
  drm/i915/dp: use the sink rates array for max sink rates
  drm/i915/dp: cache common rates with sink rates
  drm/i915/dp: do not limit rate seek when not needed
  drm/i915/dp: don't call the link parameters sink parameters
  drm/i915/dp: add functions for max common link rate and lane count
  drm/i915/mst: use max link not sink lane count
  drm/i915/dp: localize link rate index variable more
  drm/i915/dp: use readb and writeb calls for single byte DPCD access
  drm/i915/dp: read sink count to a temporary variable first

 drivers/gpu/drm/i915/intel_dp.c               | 291 ++++++++++++++------------
 drivers/gpu/drm/i915/intel_dp_link_training.c |   3 +-
 drivers/gpu/drm/i915/intel_dp_mst.c           |   4 +-
 drivers/gpu/drm/i915/intel_drv.h              |  20 +-
 4 files changed, 179 insertions(+), 139 deletions(-)

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2.1.4