[Intel-gfx] [PATCH v3 09/14] drm/i915/dp: don't call the link parameters sink parameters

[Manasi Navare]

I agree this definitely minimizes the confusion! Thanks for this patch.

Regards
Manasi

On Tue, Mar 28, 2017 at 05:59:09PM +0300, Jani Nikula wrote:
> If we modify these on the fly depending on the link conditions, don't
> pretend they are sink properties.
> 
> Some link vs. sink confusion still remains, but we'll take care of them
> in follow-up patches.
> 
> Cc: Manasi Navare <manasi.d.navare at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
 Reviewed-by: Manasi Navare <manasi.d.navare at intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dp.c  | 25 ++++++++++++-------------
>  drivers/gpu/drm/i915/intel_drv.h |  8 ++++----
>  2 files changed, 16 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 8c061c54d481..a0082a3784e8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -172,7 +172,7 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
>  	u8 source_max, sink_max;
>  
>  	source_max = intel_dig_port->max_lanes;
> -	sink_max = intel_dp->max_sink_lane_count;
> +	sink_max = intel_dp->max_link_lane_count;
>  
>  	return min(source_max, sink_max);
>  }
> @@ -326,11 +326,11 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
>  				    intel_dp->num_common_rates,
>  				    link_rate);
>  	if (index > 0) {
> -		intel_dp->max_sink_link_rate = intel_dp->common_rates[index - 1];
> -		intel_dp->max_sink_lane_count = lane_count;
> +		intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
> +		intel_dp->max_link_lane_count = lane_count;
>  	} else if (lane_count > 1) {
> -		intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
> -		intel_dp->max_sink_lane_count = lane_count >> 1;
> +		intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
> +		intel_dp->max_link_lane_count = lane_count >> 1;
>  	} else {
>  		DRM_ERROR("Link Training Unsuccessful\n");
>  		return -1;
> @@ -1561,8 +1561,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp)
>  {
>  	int len;
>  
> -	len = intel_dp_common_len_rate_limit(intel_dp,
> -					     intel_dp->max_sink_link_rate);
> +	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
>  	if (WARN_ON(len <= 0))
>  		return 162000;
>  
> @@ -1639,7 +1638,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  	uint8_t link_bw, rate_select;
>  
>  	common_len = intel_dp_common_len_rate_limit(intel_dp,
> -						    intel_dp->max_sink_link_rate);
> +						    intel_dp->max_link_rate);
>  
>  	/* No common link rates between source and sink */
>  	WARN_ON(common_len <= 0);
> @@ -3969,7 +3968,7 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
>  	test_lane_count &= DP_MAX_LANE_COUNT_MASK;
>  	/* Validate the requested lane count */
>  	if (test_lane_count < min_lane_count ||
> -	    test_lane_count > intel_dp->max_sink_lane_count)
> +	    test_lane_count > intel_dp->max_link_lane_count)
>  		return DP_TEST_NAK;
>  
>  	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
> @@ -4637,11 +4636,11 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
>  		      yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
>  
>  	if (intel_dp->reset_link_params) {
> -		/* Set the max lane count for sink */
> -		intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
> +		/* Set the max lane count for link */
> +		intel_dp->max_link_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
>  
> -		/* Set the max link rate for sink */
> -		intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp);
> +		/* Set the max link rate for link */
> +		intel_dp->max_link_rate = intel_dp_max_sink_rate(intel_dp);
>  
>  		intel_dp->reset_link_params = false;
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index ec8985b20616..9141515e4204 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -959,10 +959,10 @@ struct intel_dp {
>  	/* intersection of source and sink rates */
>  	int num_common_rates;
>  	int common_rates[DP_MAX_SUPPORTED_RATES];
> -	/* Max lane count for the sink as per DPCD registers */
> -	uint8_t max_sink_lane_count;
> -	/* Max link BW for the sink as per DPCD registers */
> -	int max_sink_link_rate;
> +	/* Max lane count for the current link */
> +	int max_link_lane_count;
> +	/* Max rate for the current link */
> +	int max_link_rate;
>  	/* sink or branch descriptor */
>  	struct intel_dp_desc desc;
>  	struct drm_dp_aux aux;
> -- 
> 2.1.4
>