[Intel-gfx] [PATCH 1/4] drm/i915: Wait for inflight writes before checking intel_engine_is_idle()

[Chris Wilson]

On Thu, Mar 30, 2017 at 11:29:40AM +0300, Mika Kuoppala wrote:
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> 
> > On Wed, Mar 29, 2017 at 10:36:16PM +0100, Chris Wilson wrote:
> >> Some GPUs may have writes inflight much longer than expected, so before
> >> declaring the GPU is idle, try to flush them using any
> >> engine->irq_seqno_barrier() if available. By allowing them to be
> >> flushed, we can be a little more confident that the GPU really is idle
> >> when we think it is!
> >> 
> >> References: https://bugs.freedesktop.org/show_bug.cgi?id=98836
> >> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> >> ---
> >>  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
> >>  1 file changed, 4 insertions(+)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> >> index c76a64483d64..ff6d0e1d1306 100644
> >> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> >> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> >> @@ -1074,6 +1074,10 @@ bool intel_engine_is_idle(struct intel_engine_cs *engine)
> >>  {
> >>  	struct drm_i915_private *dev_priv = engine->i915;
> >>  
> >> +	/* We have to allow time for writes to land from the GPU. */
> >> +	if (engine->irq_seqno_barrier)
> >> +		engine->irq_seqno_barrier(engine);
> >> +
> >
> > Problem persists so ignore this patch. 2-4 are still a nice cleanup and
> > worth persuing.
> 
> Patch 1 looked good too.

It works better as the last step, i.e. once we have decided the ring is
idle, add a little extra wait for any inflight writes. It just isn't
fixing the bug that appears to be a delayed seqno write landing after we
perform the seqno wrap. Quite mysterious, I hoped just adding a delay at
the right spot would fix it, my fear is something is amiss around reset
vs seqno-wrap.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre