[Intel-gfx] [RFC 2/4] drm/i915: Program RPCS for Broadwell

[Lionel Landwerlin]

On 02/05/17 04:49, Chris Wilson wrote:
> Currently we only configure the power gating for Skylake and above, but
> the configuration should equally apply to Broadwell and Braswell. Even
> though, there is not as much variation as for later generations, we want
> to expose control over the configuration to userspace and may want to
> opt out of the "always-enabled" setting.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/intel_lrc.c | 7 -------
>   1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 45c187abf10a..9add516d66c2 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1804,13 +1804,6 @@ make_rpcs(struct drm_i915_private *dev_priv)
>   	u32 rpcs = 0;
>   
>   	/*
> -	 * No explicit RPCS request is needed to ensure full
> -	 * slice/subslice/EU enablement prior to Gen9.
> -	*/
> -	if (INTEL_GEN(dev_priv) < 9)
> -		return 0;

Makes sense. Comments were confusing too.

> -
> -	/*
>   	 * Starting in Gen9, render power gating can leave
>   	 * slice/subslice/EU in a partially enabled state. We
>   	 * must make an explicit request through RPCS for full