[Intel-gfx] [PATCH] drm/i915/edp: Read link status after exit PSR

[Lee, Shawn C]

On Fri, Apr 28, 2017 at 03:08:53AM +0000, Lee, Shawn C wrote:
> > From: "Lee, Shawn C" <shawn.c.lee at intel.com>
> > 
> > Display driver read DPCD register 0x202, 0x203 and 0x204 to identify 
> > eDP sink status. If PSR exit is ongoing at eDP sink, and eDP source 
> > read these registers at the same time. Panel will report EQ & symbol 
> > lock not done. It will cause panel display flicking.
> > So driver have to make sure PSR already exit before read link status.
> 
> And what exactly guarantees that it will exit PSR eventually?
> 
> When read DPCD link status register, eDP can't at link train stage (after PSR exit). 

There seem to be some important word(s) missing from that sentence.
As is I don't really know what you're trying to say here.

My idea is checking SRD_STATUS before read link status registers.
If SRD_STATUS did not sent TP1, TP2, TP3 or idle pattern to sink. 
That means PSR did not at "training" stage after PSR exit. 
So host can read link status from sink and avoid unexpected result.

> TCON report EQ not done then will cause link re-training and display flicker. 
> So we read SRD_STATUS to make sure source did not send TP1, TP2, TP3 
> or idle pattern to sink side for link training.

That doesn't answer my question.

> 
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99639
> > TEST=Reboot DUT and no flicking on local display at login screen
> > 
> > Cc: Cooper Chiou <cooper.chiou at intel.com>
> > Cc: Jani Nikula <jani.nikula at intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > Cc: Jim Bride <jim.bride at intel.com>
> > Cc: Ryan Lin <ryan.lin at intel.com>
> > 
> > Signed-off-by: Shawn Lee <shawn.c.lee at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c |   34 +++++++++++++++++++++++++++++-----
> >  1 file changed, 29 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c index 08834f74d396..cc431337b2dc
> > 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4252,19 +4252,35 @@ static void 
> > intel_dp_handle_test_request(struct intel_dp *intel_dp)  }
> >  
> >  static void
> > +intel_edp_wait_PSR_exit(struct intel_dp *intel_dp) {
> > +	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	u32 srd_status, count = 100;
> > +
> > +	while (count--) {
> > +		srd_status = I915_READ(EDP_PSR_STATUS_CTL);
> > +
> > +		if ((srd_status & EDP_PSR_STATUS_SENDING_TP1) ||
> > +		    (srd_status & EDP_PSR_STATUS_SENDING_TP2_TP3) ||
> > +		    (srd_status & EDP_PSR_STATUS_SENDING_IDLE) ||
> > +		    (srd_status & EDP_PSR_STATUS_AUX_SENDING)) {
> > +			usleep_range(100, 150);
> > +		} else
> > +			return;
> > +	}
> > +}
> > +
> > +static void
> >  intel_dp_check_link_status(struct intel_dp *intel_dp)  {
> >  	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
> >  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	u8 link_status[DP_LINK_STATUS_SIZE];
> >  
> >  	
> > WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
> >  
> > -	if (!intel_dp_get_link_status(intel_dp, link_status)) {
> > -		DRM_ERROR("Failed to get link status\n");
> > -		return;
> > -	}
> > -
> >  	if (!intel_encoder->base.crtc)
> >  		return;
> >  
> > @@ -4278,6 +4294,14 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
> >  	if (!intel_dp_link_params_valid(intel_dp))
> >  		return;
> >  
> > +	if (is_edp(intel_dp) && dev_priv->psr.enabled)
> > +		intel_edp_wait_PSR_exit(intel_dp);
> > +
> > +	if (!intel_dp_get_link_status(intel_dp, link_status)) {
> > +		DRM_ERROR("Failed to get link status\n");
> > +		return;
> > +	}
> > +
> >  	/* Retrain if Channel EQ or CR not ok */
> >  	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
> >  		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
> > --
> > 1.7.9.5
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC

--
Ville Syrjälä
Intel OTC