[Intel-gfx] [RFC 2/7] drm/i915: Program gen3- watermarks atomically

Maarten Lankhorst maarten.lankhorst at linux.intel.com
Thu May 4 11:41:28 UTC 2017


With the atomic watermark calculations calculate intermediary watermark
values and update the watermarks atomically.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |   5 ++
 drivers/gpu/drm/i915/intel_drv.h |   2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 103 +++++++++++++++++++++++++++++++++------
 3 files changed, 95 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 91b945cd39f9..7af4f908b2cd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1793,6 +1793,10 @@ struct g4x_wm_values {
 	bool fbc_en;
 };
 
+struct i9xx_wm_values {
+	bool cxsr;
+};
+
 struct skl_ddb_entry {
 	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
 };
@@ -2422,6 +2426,7 @@ struct drm_i915_private {
 			struct skl_wm_values skl_hw;
 			struct vlv_wm_values vlv;
 			struct g4x_wm_values g4x;
+			struct i9xx_wm_values i9xx;
 		};
 
 		uint8_t max_level;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d9e49f2b3c22..73e74fc7383c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -600,7 +600,7 @@ struct intel_crtc_wm_state {
 			struct g4x_wm_state optimal;
 		} g4x;
 		struct {
-			struct i9xx_wm_state optimal;
+			struct i9xx_wm_state optimal, intermediate;
 		} i9xx;
 	};
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0c933cfad02c..c39f63aff4a5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -433,6 +433,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 		dev_priv->wm.vlv.cxsr = enable;
 	else if (IS_G4X(dev_priv))
 		dev_priv->wm.g4x.cxsr = enable;
+	else if (INTEL_GEN(dev_priv) <= 4)
+		dev_priv->wm.i9xx.cxsr = enable;
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 
 	return ret;
@@ -2317,6 +2319,44 @@ static int i9xx_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
+static int i9xx_compute_intermediate_wm(struct drm_device *dev,
+				       struct intel_crtc *intel_crtc,
+				       struct intel_crtc_state *newstate)
+{
+	struct i9xx_wm_state *intermediate = &newstate->wm.i9xx.intermediate;
+	const struct drm_crtc_state *old_drm_state =
+		drm_atomic_get_old_crtc_state(newstate->base.state, &intel_crtc->base);
+	const struct i9xx_wm_state *old = &to_intel_crtc_state(old_drm_state)->wm.i9xx.optimal;
+	const struct i9xx_wm_state *optimal = &newstate->wm.i9xx.optimal;
+
+	/*
+	 * Start with the final, target watermarks, then combine with the
+	 * currently active watermarks to get values that are safe both before
+	 * and after the vblank.
+	 */
+	*intermediate = *optimal;
+	if (newstate->disable_cxsr)
+		intermediate->cxsr = false;
+
+	if (!newstate->base.active ||
+	    drm_atomic_crtc_needs_modeset(&newstate->base))
+		goto out;
+
+	intermediate->plane_wm = min(old->plane_wm, optimal->plane_wm);
+	intermediate->sr.plane = min(old->sr.plane, optimal->sr.plane);
+
+out:
+	/*
+	 * If our intermediate WM are identical to the final WM, then we can
+	 * omit the post-vblank programming; only update if it's different.
+	 */
+	if (newstate->base.active &&
+	    memcmp(intermediate, optimal, sizeof(*intermediate)) != 0)
+		newstate->wm.need_postvbl_update = true;
+
+	return 0;
+}
+
 void i9xx_wm_get_hw_state(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -2345,17 +2385,15 @@ void i9xx_wm_get_hw_state(struct drm_device *dev)
 	}
 }
 
-static void i9xx_update_wm(struct intel_crtc *crtc)
+static void i9xx_program_watermarks(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_crtc *crtc;
 	uint32_t fwater_lo;
 	uint32_t fwater_hi;
 	int cwm, srwm = -1;
 	int planea_wm, planeb_wm;
 	struct intel_crtc *enabled = NULL;
 
-	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
-
 	crtc = intel_get_crtc_for_plane(dev_priv, 0);
 	planea_wm = crtc->wm.active.i9xx.plane_wm;
 	if (intel_crtc_active(crtc))
@@ -2381,7 +2419,7 @@ static void i9xx_update_wm(struct intel_crtc *crtc)
 	cwm = 2;
 
 	/* Play safe and disable self-refresh before adjusting watermarks. */
-	intel_set_memory_cxsr(dev_priv, false);
+	_intel_set_memory_cxsr(dev_priv, false);
 
 	/* Calc sr entries for one plane configs */
 	if (enabled) {
@@ -2408,19 +2446,17 @@ static void i9xx_update_wm(struct intel_crtc *crtc)
 	I915_WRITE(FW_BLC2, fwater_hi);
 
 	if (enabled)
-		intel_set_memory_cxsr(dev_priv, true);
+		_intel_set_memory_cxsr(dev_priv, true);
+
+	dev_priv->wm.i9xx.cxsr = enabled;
 }
 
-static void i845_update_wm(struct intel_crtc *crtc)
+static void i845_program_watermarks(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	uint32_t fwater_lo;
 	int planea_wm;
 
-	if (!intel_crtc_active(crtc))
-		return;
-
-	crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
 	planea_wm = crtc->wm.active.i9xx.plane_wm;
 
 	fwater_lo = I915_READ(FW_BLC) & ~0xfff;
@@ -2431,6 +2467,41 @@ static void i845_update_wm(struct intel_crtc *crtc)
 	I915_WRITE(FW_BLC, fwater_lo);
 }
 
+
+static void i9xx_initial_watermarks(struct intel_atomic_state *state,
+				   struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+
+	mutex_lock(&dev_priv->wm.wm_mutex);
+	crtc->wm.active.i9xx = crtc_state->wm.i9xx.intermediate;
+	if (INTEL_INFO(dev_priv)->num_pipes == 1)
+		i845_program_watermarks(intel_crtc);
+	else
+		i9xx_program_watermarks(dev_priv);
+	mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
+static void i9xx_optimize_watermarks(struct intel_atomic_state *state,
+				    struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
+
+	if (!crtc_state->wm.need_postvbl_update)
+		return;
+
+	mutex_lock(&dev_priv->wm.wm_mutex);
+	intel_crtc->wm.active.i9xx = crtc_state->wm.i9xx.optimal;
+	if (INTEL_INFO(dev_priv)->num_pipes == 1)
+		i845_program_watermarks(intel_crtc);
+	else
+		i9xx_program_watermarks(dev_priv);
+	mutex_unlock(&dev_priv->wm.wm_mutex);
+}
+
 /* latency must be in 0.1us units. */
 static unsigned int ilk_wm_method1(unsigned int pixel_rate,
 				   unsigned int cpp,
@@ -8743,17 +8814,21 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		dev_priv->display.update_wm = i965_update_wm;
 	} else if (IS_GEN3(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
-		dev_priv->display.update_wm = i9xx_update_wm;
+		dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
+
+		dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+		dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 
 		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
 	} else if (IS_GEN2(dev_priv)) {
 		dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
+		dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm;
+		dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+		dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks;
 
 		if (INTEL_INFO(dev_priv)->num_pipes == 1) {
-			dev_priv->display.update_wm = i845_update_wm;
 			dev_priv->display.get_fifo_size = i845_get_fifo_size;
 		} else {
-			dev_priv->display.update_wm = i9xx_update_wm;
 			dev_priv->display.get_fifo_size = i830_get_fifo_size;
 		}
 	} else {
-- 
2.9.3



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