[Intel-gfx] [PATCH] drm/i915: Restore GT performance in headless mode with DMC loaded

[Chris Wilson]

On Fri, May 05, 2017 at 12:43:21PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> 
> It seems that the DMC likes to transition between the DC states
> a lot when there are no connected displays (no active power
> domains) during simple command submission.
> 
> This frantic activity on DC states has a terrible impact on the
> performance of the overall chip with huge latencies observed in
> the interrupt handlers and elsewhere. Simple tests like
> igt/gem_latency -n 0 are slowed down by a factor of eight.
> 
> Work around it by grabbing a modeset display power domain whilst
> there is any GT activity. This seems to be effective in making
> the DMC keep its paws off the chip.
> 
> On the other hand this may have a negative impact on the overall
> power budget of the chip and so could still affect performance.

Please add this as a comment to the code, I think in mark_busy(). I
don't think this w/a will remain applicable forever and so merits a
continual reminder and being discussed again in future.
 
> This version limits the workaround got SKL GT3 and GT4 parts but
> this is just due the absence of testing on other platforms. It
> is possible we will have to apply it wider.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100572
> Testcase: igt/gem_exec_nop/headless
> Cc: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h         | 5 +++++
>  drivers/gpu/drm/i915/i915_gem.c         | 4 ++++
>  drivers/gpu/drm/i915/i915_gem_request.c | 3 +++
>  3 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 320c16df1c9c..4d58e2e28c2f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2990,6 +2990,11 @@ intel_info(const struct drm_i915_private *dev_priv)
>  
>  #define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)
>  
> +#define NEEDS_CSR_GT_PERF_WA(dev_priv) \
> +	HAS_CSR(dev_priv) && \
> +	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) && \
> +	(dev_priv)->csr.dmc_payload

csr.dmc_payload is a bit of a surprise, but looks correct.

Acked-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre