[Intel-gfx] [RFC] drm/i915: Allow the UMD to configure their own power clock state

[Mika Kuoppala]

Oscar Mateo <oscar.mateo at intel.com> writes:

> This allows userspace to shutdown slices at will for performance/power reasons
> (because it doesn't have a use for more slices).
>
> Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 402769d..17ff88d 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -628,6 +628,7 @@ static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
>  static int gen8_init_workarounds(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> +	int ret;
>  
>  	WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>  
> @@ -673,6 +674,11 @@ static int gen8_init_workarounds(struct intel_engine_cs *engine)
>  			    GEN6_WIZ_HASHING_MASK,
>  			    GEN6_WIZ_HASHING_16x4);
>  
> +	/* Allow the UMD to configure their own power clock state */
> +	ret = wa_ring_whitelist_reg(engine, GEN8_R_PWR_CLK_STATE);
> +	if (ret)
> +		return ret;
> +

How will the different userspace clients coordinate with the slice
state? I guess in another words, is this part of the context?

-Mika


>  	return 0;
>  }
>  
> @@ -841,6 +847,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	if (ret)
>  		return ret;
>  
> +	/* Allow the UMD to configure their own power clock state */
> +	ret = wa_ring_whitelist_reg(engine, GEN8_R_PWR_CLK_STATE);
> +	if (ret)
> +		return ret;
> +
>  	return 0;
>  }
>  
> -- 
> 1.9.1
>
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