[Intel-gfx] [PATCH 11/17] drm/i915: disable GTT cache for 2M/1G pages

[Chris Wilson]

On Tue, May 16, 2017 at 01:04:38PM +0300, Ville Syrjälä wrote:
> On Tue, May 16, 2017 at 09:29:42AM +0100, Matthew Auld wrote:
> > When SW enables the use of 2M/1G pages, it must disable the GTT cache.
> > 
> > Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------
> >  1 file changed, 6 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ef0e9f8d4dbd..b39b8d394179 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -8178,10 +8178,10 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
> >  
> >  	/*
> >  	 * WaGttCachingOffByDefault:bdw
> > -	 * GTT cache may not work with big pages, so if those
> > -	 * are ever enabled GTT cache may need to be disabled.
> > +	 * The GTT cache must be disabled if the system is planning to use
> > +	 * 2M/1G pages.
> >  	 */
> > -	I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
> > +	I915_WRITE(HSW_GTT_CACHE_EN, 0);
> >  
> >  	/* WaKVMNotificationOnConfigChange:bdw */
> >  	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
> > @@ -8457,10 +8457,10 @@ static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
> >  	gen8_set_l3sqc_credits(dev_priv, 38, 2);
> >  
> >  	/*
> > -	 * GTT cache may not work with big pages, so if those
> > -	 * are ever enabled GTT cache may need to be disabled.
> > +	 * The GTT cache must be disabled if the system is planning to use
> > +	 * 2M/1G pages.
> >  	 */
> > -	I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
> > +	I915_WRITE(HSW_GTT_CACHE_EN, 0);
> >  }
> 
> Should we perhaps have a modparam to make it easier to evaluate
> whether big pages are actually beneficial or not? If so, it should also
> affect whether we enable the the GTT cache or not.

If we are sticking to only using it on bdw 48b, then ppgtt=4? It doesn't
seem a good idea for a long term modparam, but who wants to keep a
modparam around where users might find it?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre