[Intel-gfx] [PATCH v2 4/5] drm/i915/gvt: Dmabuf support for GVT-g
Xiaoguang Chen
xiaoguang.chen at intel.com
Thu May 18 09:50:04 UTC 2017
dmabuf for GVT-g can be exported to users who can use the dmabuf to show
the desktop of vm which use intel vgpu.
Currently we provide query and create new dmabuf operations.
Users of dmabuf can cache some created dmabufs and related information
such as the framebuffer's address, size, tiling mode, width, height etc.
When refresh the screen first query the currnet vgpu's frambuffer and
compare with the cached ones(address, size, tiling, width, height etc)
if found one then reuse the found dmabuf to gain performance improvment.
If there is no dmabuf created yet or not found in the cached dmabufs then
need to create a new dmabuf. To create a dmabuf first a gem object will
be created and the backing storage of this gem object is the vgpu's
framebuffer(primary/cursor). Then associate this gem object to a dmabuf
and export this dmabuf. A file descriptor will be generated for this
dmabuf and this file descriptor can be sent to user space to do display.
Signed-off-by: Xiaoguang Chen <xiaoguang.chen at intel.com>
---
drivers/gpu/drm/i915/gvt/Makefile | 2 +-
drivers/gpu/drm/i915/gvt/dmabuf.c | 321 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gvt/dmabuf.h | 44 ++++++
drivers/gpu/drm/i915/gvt/gvt.h | 3 +
include/uapi/drm/i915_drm.h | 21 +++
5 files changed, 390 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h
diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile
index 192ca26..e480f7d 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -2,7 +2,7 @@ GVT_DIR := gvt
GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
- fb_decoder.o
+ fb_decoder.o dmabuf.o
ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall
i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
new file mode 100644
index 0000000..3358e6f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Zhiyuan Lv <zhiyuan.lv at intel.com>
+ *
+ * Contributors:
+ * Xiaoguang Chen <xiaoguang.chen at intel.com>
+ */
+
+#include <linux/dma-buf.h>
+#include <drm/drmP.h>
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define GEN8_DECODE_PTE(pte) \
+ ((dma_addr_t)(((((u64)pte) >> 12) & 0x7ffffffULL) << 12))
+
+static struct sg_table *intel_vgpu_gem_get_pages(
+ struct drm_i915_gem_object *obj)
+{
+ struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+ struct intel_gvt *gvt = dev_priv->gvt;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ int i, ret;
+ gen8_pte_t __iomem *gtt_entries;
+ struct intel_vgpu *vgpu;
+ unsigned int fb_gma = 0, fb_size = 0;
+ bool found = false;
+
+ mutex_lock(&gvt->lock);
+ for_each_active_vgpu(gvt, vgpu, i) {
+ if (vgpu->obj_dmabuf == obj) {
+ fb_gma = vgpu->plane_info->start;
+ fb_size = vgpu->plane_info->size;
+ found = true;
+ break;
+ }
+ }
+ mutex_unlock(&gvt->lock);
+
+ if (!found) {
+ gvt_vgpu_err("no vgpu found\n");
+ return NULL;
+ }
+
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st) {
+ ret = -ENOMEM;
+ return ERR_PTR(ret);
+ }
+
+ ret = sg_alloc_table(st, fb_size, GFP_KERNEL);
+ if (ret) {
+ kfree(st);
+ return ERR_PTR(ret);
+ }
+ gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+ (fb_gma >> PAGE_SHIFT);
+ for_each_sg(st->sgl, sg, fb_size, i) {
+ sg->offset = 0;
+ sg->length = PAGE_SIZE;
+ sg_dma_address(sg) =
+ GEN8_DECODE_PTE(readq(>t_entries[i]));
+ sg_dma_len(sg) = PAGE_SIZE;
+ }
+
+ return st;
+}
+
+static void intel_vgpu_gem_put_pages(struct drm_i915_gem_object *obj,
+ struct sg_table *pages)
+{
+ struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+ struct intel_gvt *gvt = dev_priv->gvt;
+ int i;
+ struct intel_vgpu *vgpu;
+
+ mutex_lock(&gvt->lock);
+ for_each_active_vgpu(gvt, vgpu, i) {
+ if (vgpu->obj_dmabuf == obj) {
+ kfree(vgpu->plane_info);
+ break;
+ }
+ }
+ mutex_unlock(&gvt->lock);
+
+ sg_free_table(pages);
+ kfree(pages);
+
+ i915_gem_object_unpin_pages(obj);
+}
+
+static const struct drm_i915_gem_object_ops intel_vgpu_gem_ops = {
+ .get_pages = intel_vgpu_gem_get_pages,
+ .put_pages = intel_vgpu_gem_put_pages,
+};
+
+static struct drm_i915_gem_object *intel_vgpu_create_gem(struct drm_device *dev,
+ struct intel_vgpu *vgpu)
+{
+ struct drm_i915_private *pri = dev->dev_private;
+ struct drm_i915_gem_object *obj;
+ struct intel_vgpu_plane_info *info = vgpu->plane_info;
+
+ obj = i915_gem_object_alloc(pri);
+ if (obj == NULL)
+ return NULL;
+
+ drm_gem_private_object_init(dev, &obj->base,
+ info->size << PAGE_SHIFT);
+ i915_gem_object_init(obj, &intel_vgpu_gem_ops);
+
+ obj->base.read_domains = I915_GEM_DOMAIN_GTT;
+ obj->base.write_domain = 0;
+
+ if (IS_SKYLAKE(pri)) {
+ unsigned int tiling_mode = 0;
+
+ switch (info->tiled << 10) {
+ case PLANE_CTL_TILED_LINEAR:
+ tiling_mode = I915_TILING_NONE;
+ break;
+ case PLANE_CTL_TILED_X:
+ tiling_mode = I915_TILING_X;
+ break;
+ case PLANE_CTL_TILED_Y:
+ tiling_mode = I915_TILING_Y;
+ break;
+ default:
+ gvt_vgpu_err("tile %d not supported\n", info->tiled);
+ }
+ obj->tiling_and_stride = tiling_mode | info->stride;
+ } else {
+ obj->tiling_and_stride = info->tiled ? I915_TILING_X : 0;
+ }
+
+ return obj;
+}
+
+static struct intel_vgpu_plane_info *intel_vgpu_get_plane_info(
+ struct drm_device *dev,
+ struct intel_vgpu *vgpu, int plane_id)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_vgpu_primary_plane_format *p;
+ struct intel_vgpu_cursor_plane_format *c;
+ struct intel_vgpu_plane_info *info;
+
+ info = kmalloc(sizeof(*info), GFP_KERNEL);
+ if (!info)
+ return NULL;
+
+ if (plane_id == INTEL_GVT_PLANE_PRIMARY) {
+ p = (struct intel_vgpu_primary_plane_format *)
+ intel_vgpu_decode_plane(dev, vgpu, plane_id);
+ if (p != NULL) {
+ info->start = p->base;
+ info->width = p->width;
+ info->height = p->height;
+ info->stride = p->stride;
+ info->drm_format = p->drm_format;
+ info->tiled = p->tiled;
+ info->size = (((p->stride * p->height * p->bpp) / 8) +
+ (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+ } else {
+ kfree(info);
+ gvt_vgpu_err("invalid primary plane\n");
+ return NULL;
+ }
+ } else if (plane_id == INTEL_GVT_PLANE_CURSOR) {
+ c = (struct intel_vgpu_cursor_plane_format *)
+ intel_vgpu_decode_plane(dev, vgpu, plane_id);
+ if (c != NULL) {
+ info->start = c->base;
+ info->width = c->width;
+ info->height = c->height;
+ info->stride = c->width * (c->bpp / 8);
+ info->tiled = 0;
+ info->x_pos = c->x_pos;
+ info->y_pos = c->y_pos;
+ info->size = (((info->stride * c->height * c->bpp) / 8)
+ + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+ } else {
+ kfree(info);
+ gvt_vgpu_err("invalid cursor plane\n");
+ return NULL;
+ }
+ } else {
+ kfree(info);
+ gvt_vgpu_err("invalid plane id:%d\n", plane_id);
+ return NULL;
+ }
+
+ if (info->size == 0) {
+ kfree(info);
+ gvt_vgpu_err("fb size is zero\n");
+ return NULL;
+ }
+
+ if (info->start & (PAGE_SIZE - 1)) {
+ kfree(info);
+ gvt_vgpu_err("Not aligned fb address:0x%x\n", info->start);
+ return NULL;
+ }
+ if (((info->start >> PAGE_SHIFT) + info->size) >
+ ggtt_total_entries(&dev_priv->ggtt)) {
+ kfree(info);
+ gvt_vgpu_err("Invalid GTT offset or size\n");
+ return NULL;
+ }
+
+ if (!intel_gvt_ggtt_validate_range(vgpu, info->start, info->size)) {
+ kfree(info);
+ gvt_vgpu_err("invalid gma addr\n");
+ return NULL;
+ }
+
+ return info;
+}
+
+int intel_vgpu_query_dmabuf(struct intel_vgpu *vgpu, void *args)
+{
+ struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
+ struct intel_vgpu_dmabuf *gvt_dmabuf = args;
+ struct intel_vgpu_plane_info *info;
+
+ info = intel_vgpu_get_plane_info(dev, vgpu, gvt_dmabuf->plane_id);
+ if (info == NULL)
+ return -EINVAL;
+
+ vgpu->plane_info = info;
+
+ gvt_dmabuf->drm_format = info->drm_format;
+ gvt_dmabuf->width = info->width;
+ gvt_dmabuf->height = info->height;
+ gvt_dmabuf->stride = info->stride;
+ gvt_dmabuf->start = info->start;
+ gvt_dmabuf->x_pos = info->x_pos;
+ gvt_dmabuf->y_pos = info->y_pos;
+ gvt_dmabuf->size = info->size;
+ gvt_dmabuf->tiled = info->tiled;
+
+ return 0;
+}
+
+int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args)
+{
+ struct dma_buf *dmabuf;
+ struct drm_i915_gem_object *obj;
+ struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
+ struct intel_vgpu_dmabuf *gvt_dmabuf = args;
+ struct intel_vgpu_plane_info *info;
+ int ret;
+
+ info = intel_vgpu_get_plane_info(dev, vgpu, gvt_dmabuf->plane_id);
+ if (info == NULL)
+ return -EINVAL;
+
+ vgpu->plane_info = info;
+ obj = intel_vgpu_create_gem(dev, vgpu);
+ if (obj == NULL) {
+ gvt_vgpu_err("create gvt gem obj failed:%d\n", vgpu->id);
+ return -EINVAL;
+ }
+ vgpu->obj_dmabuf = obj;
+
+ ret = i915_gem_object_pin_pages(obj);
+ if (ret) {
+ i915_gem_object_free(obj);
+ gvt_vgpu_err("pin pages failed\n");
+ return -EINVAL;
+ }
+
+ dmabuf = i915_gem_prime_export(dev, &obj->base, DRM_CLOEXEC | DRM_RDWR);
+
+ if (IS_ERR(dmabuf)) {
+ gvt_vgpu_err("export dma-buf failed\n");
+ return -EINVAL;
+ }
+
+ ret = dma_buf_fd(dmabuf, DRM_CLOEXEC | DRM_RDWR);
+ if (ret < 0) {
+ gvt_vgpu_err("create dma-buf fd failed ret:%d\n", ret);
+ return -EINVAL;
+ }
+ gvt_dmabuf->fd = ret;
+
+ gvt_dmabuf->drm_format = info->drm_format;
+ gvt_dmabuf->width = info->width;
+ gvt_dmabuf->height = info->height;
+ gvt_dmabuf->stride = info->stride;
+ gvt_dmabuf->start = info->start;
+ gvt_dmabuf->x_pos = info->x_pos;
+ gvt_dmabuf->y_pos = info->y_pos;
+ gvt_dmabuf->size = info->size;
+ gvt_dmabuf->tiled = info->tiled;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.h b/drivers/gpu/drm/i915/gvt/dmabuf.h
new file mode 100644
index 0000000..a411fc6
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.h
@@ -0,0 +1,44 @@
+
+/*
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifndef _GVT_DMABUF_H_
+#define _GVT_DMABUF_H_
+
+struct intel_vgpu_plane_info {
+ unsigned int drm_format;
+ unsigned int width;
+ unsigned int height;
+ unsigned int stride;
+ unsigned int start;
+ unsigned int x_pos;
+ unsigned int y_pos;
+ unsigned int size;
+ unsigned int tiled;
+};
+
+int intel_vgpu_query_dmabuf(struct intel_vgpu *vgpu, void *args);
+int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args);
+
+#endif
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index c42266c..a553120 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -47,6 +47,7 @@
#include "render.h"
#include "cmd_parser.h"
#include "fb_decoder.h"
+#include "dmabuf.h"
#define GVT_MAX_VGPU 8
@@ -186,6 +187,8 @@ struct intel_vgpu {
atomic_t released;
} vdev;
#endif
+ struct intel_vgpu_plane_info *plane_info;
+ struct drm_i915_gem_object *obj_dmabuf;
};
struct intel_gvt_gm {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ece8e2b..cde4f8e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1445,6 +1445,27 @@ enum drm_i915_perf_record_type {
#define INTEL_GVT_PLANE_SPRITE 2
#define INTEL_GVT_PLANE_CURSOR 3
+/**
+ * Ioctl to query plane info or create dma-buf
+ */
+#define INTEL_VGPU_QUERY_DMABUF 0
+#define INTEL_VGPU_GENERATE_DMABUF 1
+
+struct intel_vgpu_dmabuf {
+ __u32 plane_id;
+ /* out */
+ __u32 fd;
+ __u32 drm_format;
+ __u32 width;
+ __u32 height;
+ __u32 stride;
+ __u32 start;
+ __u32 x_pos;
+ __u32 y_pos;
+ __u32 size;
+ __u32 tiled;
+};
+
#if defined(__cplusplus)
}
#endif
--
1.9.1
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