[Intel-gfx] [PATCH 1/2] drm/i915/skl: New ddb allocation algorithm

[Mahesh Kumar]

Hi,


On Thursday 18 May 2017 04:45 PM, Lankhorst, Maarten wrote:
> Mahesh Kumar schreef op do 18-05-2017 om 15:39 [+0530]:
>> From: "Kumar, Mahesh" <mahesh1.kumar at intel.com>
>>
>> This patch implements new DDB allocation algorithm as per HW team
>> recommendation. This algo takecare of scenario where we allocate less
>> DDB
>> for the planes with lower relative pixel rate, but they require more
>> DDB
>> to work.
>> It also takes care of enabling same watermark level for each
>> plane in crtc, for efficient power saving.
>>
>> Changes since v1:
>>   - Rebase on top of Paulo's patch series
>>
>> Changes since v2:
>>   - Fix the for loop condition to enable WM
>>
>> Changes since v3:
>>   - Fix crash in cursor i-g-t reported by Maarten
>>   - Rebase after addressing Paulo's comments
>>   - Few other ULT fixes
>> Changes since v4:
>>   - Rebase on drm-tip
>>   - Added separate function to enable WM levels
>> Changes since v5:
>>   - Fix a crash identified in skl-6770HQ system
>> Changes since v6:
>>   - Address review comments from Matt
>> Changes since v7:
>>   - Fix failure return in skl_compute_plane_wm (Matt)
>>   - fix typo
>>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar at intel.com>
>> Reviewed-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> Hm just to be sure it works as intended I tested this against full kms,
> testsuite and it seems to cause FIFO underruns on my KBL with the
> kms_atomic_transition test.
>
> I think we shouldn't merge this until all those fifo underruns have
> been fixed, especially because FIFO underruns may result in a complete
> lockup of the gpu.
Thanks for trying this out Maarten,
I don't have access to KBL board now. Will try to find one & debug this 
further.

-Mahesh
> Sorry for the bad news,
> Maarten