[Intel-gfx] [PATCH] drm/i915: Work around for underrun when enabling pipe scaler in GLK

[Mahesh Kumar]

Hi,


On Monday 08 May 2017 02:20 PM, Ander Conselvan de Oliveira wrote:
> In Geminilake, a FIFO underrun happens the first time a pipe scaler is
> enabled after boot/resume from suspend. Disabling DPF clock gating in
> the respective CLKGATE_DIS_PSL register prior to enabling the scaler
> works around the issue.
Is BSpec link or workaround number available for this?

-Mahesh
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h      |  8 ++++++++
>   drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++++++++
>   2 files changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 524fdfd..3157c39 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3424,6 +3424,14 @@ enum {
>   #define   PWM2_GATING_DIS		(1 << 14)
>   #define   PWM1_GATING_DIS		(1 << 13)
>   
> +#define _CLKGATE_DIS_PSL_A		0x46520
> +#define _CLKGATE_DIS_PSL_B		0x46524
> +#define _CLKGATE_DIS_PSL_C		0x46528
> +#define   DPF_GATING_DIS		(1 << 10)
> +
> +#define CLKGATE_DIS_PSL(pipe) \
> +	_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
> +
>   /*
>    * Display engine regs
>    */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 85b9e2f5..c24acdd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3176,6 +3176,7 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
>   static void skl_detach_scalers(struct intel_crtc *intel_crtc)
>   {
>   	struct intel_crtc_scaler_state *scaler_state;
> +	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>   	int i;
>   
>   	scaler_state = &intel_crtc->config->scaler_state;
> @@ -3185,6 +3186,14 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc)
>   		if (!scaler_state->scalers[i].in_use)
>   			skl_detach_scaler(intel_crtc, i);
>   	}
> +
> +	if (IS_GEMINILAKE(dev_priv)) {
> +		u32 tmp;
> +
> +		tmp = I915_READ(CLKGATE_DIS_PSL(intel_crtc->pipe));
> +		tmp &= ~DPF_GATING_DIS;
> +		I915_WRITE(CLKGATE_DIS_PSL(intel_crtc->pipe), tmp);
> +	}
>   }
>   
>   u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
> @@ -4763,6 +4772,14 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
>   		if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
>   			return;
>   
> +		if (IS_GEMINILAKE(dev_priv)) {
> +			u32 tmp;
> +
> +			tmp = I915_READ(CLKGATE_DIS_PSL(crtc->pipe));
> +			tmp |= DPF_GATING_DIS;
> +			I915_WRITE(CLKGATE_DIS_PSL(crtc->pipe), tmp);
> +		}
> +
>   		id = scaler_state->scaler_id;
>   		I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
>   			PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);