[Intel-gfx] [PATCH v2 1/2] drm/i915/skl: New ddb allocation algorithm

[Maarten Lankhorst]

Hey,

Op 25-05-17 om 08:28 schreef Mahesh Kumar:
> From: "Kumar, Mahesh" <mahesh1.kumar at intel.com>
>
> This patch implements new DDB allocation algorithm as per HW team
> recommendation. This algo takecare of scenario where we allocate less DDB
> for the planes with lower relative pixel rate, but they require more DDB
> to work.
> It also takes care of enabling same watermark level for each
> plane in crtc, for efficient power saving.
>
> Changes since v1:
>  - Rebase on top of Paulo's patch series
>
> Changes since v2:
>  - Fix the for loop condition to enable WM
>
> Changes since v3:
>  - Fix crash in cursor i-g-t reported by Maarten
>  - Rebase after addressing Paulo's comments
>  - Few other ULT fixes
> Changes since v4:
>  - Rebase on drm-tip
>  - Added separate function to enable WM levels
> Changes since v5:
>  - Fix a crash identified in skl-6770HQ system
> Changes since v6:
>  - Address review comments from Matt
> Changes since v7:
>  - Fix failure return in skl_compute_plane_wm (Matt)
>  - fix typo
> Changes since v8:
>  - Always check cursor wm enable irrespective of total_data_rate

This fixes most tests, but when testing on f3-kbl I still get some new fifo underruns,
one early during boot, one when shutting down lightdm and one during kms_atomic_transition.plane-primary-toggle-with-vblank-wait

Oddly enough, kms_atomic_transition.plane-primary-toggle-with-vblank-wait
fails without these patches applied too with

[   57.303525] [drm:skl_compute_wm [i915]] Requested display configuration exceeds system watermark limitations
[   57.303539] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] blocks required = 4/0, lines required = 1/31

Very weird, but those test failure upstream are still better than FIFO underruns. :/

~Maarten