[Intel-gfx] [PATCH 1/3] drm/i915: Wa#0893 is defined per platform.

[Rodrigo Vivi]

No detection will ever be needed. So let's simplify
and clean it up.

Cc: Mahesh Kumar <mahesh1.kumar at intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  4 ++++
 drivers/gpu/drm/i915/intel_pm.c | 21 ++-------------------
 2 files changed, 6 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d2a5749..5abeb3f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2904,6 +2904,10 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
 	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 
+/* WA#0893 */
+#define NEEDS_WaIncreaseMemoryBW(dev_priv)	(IS_GEN9_BC(dev_priv) || \
+						 IS_BROXTON(dev_priv))
+
 /*
  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
  * even when in MSI mode. This results in spurious interrupt warnings if the
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32b3b3e..919235c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3532,21 +3532,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
-/*
- * FIXME: We still don't have the proper code detect if we need to apply the WA,
- * so assume we'll always need it in order to avoid underruns.
- */
-static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
-{
-	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
-
-	/* WA#0893: GEN9:ALL */
-	if (IS_GEN9(dev_priv))
-		return true;
-
-	return false;
-}
-
 static bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
@@ -3694,7 +3679,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 
 		latency = dev_priv->wm.skl_latency[level];
 
-		if (skl_needs_memory_bw_wa(intel_state) &&
+		if (NEEDS_WaIncreaseMemoryBW(dev_priv) &&
 		    plane->base.state->fb->modifier ==
 		    I915_FORMAT_MOD_X_TILED)
 			latency += 15;
@@ -4265,9 +4250,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	uint32_t plane_pixel_rate;
 	uint_fixed_16_16_t y_tile_minimum;
 	uint32_t y_min_scanlines;
-	struct intel_atomic_state *state =
-		to_intel_atomic_state(cstate->base.state);
-	bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
+	bool apply_memory_bw_wa = NEEDS_WaIncreaseMemoryBW(dev_priv);
 	bool y_tiled, x_tiled;
 
 	if (latency == 0 ||
-- 
1.9.1