[Intel-gfx] [PATCH 2/3] drm/i915/glk: WA#0893: Also apply memory bw wa to Geminilake.

[Vivi, Rodrigo]

On Mon, 2017-05-29 at 11:26 +0300, Ander Conselvan De Oliveira wrote:
> On Fri, 2017-05-26 at 16:23 -0700, Rodrigo Vivi wrote:
> > According to spec this WA is needed for every gen9.
> 
> Actually GLK has a gen10 display, so the gen9 workarounds don't apply.

Oh, indeed!

Please ignore this patch.

> 
> Ander
> 
> > 
> > Cc:Arthur Runyan <arthur.j.runyan at intel.com>
> > Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h | 5 ++---
> >  1 file changed, 2 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 5abeb3f..7a5f2e4 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2904,9 +2904,8 @@ static inline struct scatterlist *__sg_next(struct scatterlist *sg)
> >  #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> >  	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
> >  
> > -/* WA#0893 */
> > -#define NEEDS_WaIncreaseMemoryBW(dev_priv)	(IS_GEN9_BC(dev_priv) || \
> > -						 IS_BROXTON(dev_priv))
> > +/* WA#0893: GEN9:ALL */
> > +#define NEEDS_WaIncreaseMemoryBW(dev_priv)	(IS_GEN9(dev_priv))
> >  
> >  /*
> >   * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts