[Intel-gfx] [PATCH] drm/i915: set minimum CD clock to twice the BCLK.

[Prusty, Subhransu S]

> >>>>>> b/drivers/gpu/drm/i915/intel_cdclk.c index
> >>>>>> e8884c2ade98..185a70f0921c
> >>>>>> 100644
> >>>>>> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> >>>>>> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> >>>>>> @@ -1920,7 +1920,7 @@ int intel_crtc_compute_min_cdclk(const struct
> >>>>>> intel_crtc_state *crtc_state) /* According to BSpec, "The CD clock
> >>>>>> frequency must be at least twice * the frequency of the Azalia
> >>>>>> BCLK." and BCLK is 96 MHz by default. */
> >>>>>> -	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> >>>>>> +	if (INTEL_GEN(dev_priv) >= 9)
> >>>>> Why should cdclk be increased when audio is not being enabled?
> >>>> Indeed. I can easily imagine a counter-bug reporting excessive cdclk
> >>>> when audio is not enabled.
> >>> During bootup time audio driver is trying to acquire HDA audio power well
> inside i915 and then it will send HDA verb commands.
> >>> since cdclk is lower than 96Mhz  HDA will not comeup resulting in timeout.
> This was working fine  before SKL/APL since there was no 2 PPC .
> >>>
> >>> Is it ok to bump  up cdclk while bootup of system/HDA and then reduce to
> needed CDCLK?
> >> I think it is worth exploring, do you have code to test whether it
> >> solves this particular issue?
> > No i don't have test code for this but what i learned from other OS that
> > glk run at 148000 and cnl 96000*2 due to this limitation all the time.
> 
> Is there an HSD for this? It's a bit surprising you can't even probe the
> driver without a higher cdclk.

Hi Jani,

The driver probe happens based on vendor id and revision id read from the codec, and
the vendor/revision are read from the codec over HDA bus. 

Since codecs are enumerable, without successful match of vendor/revision id  the driver
probe will not happen.

Regards,
Subhransu

> 
> BR,
> Jani.
> 
> >
> > @Shubhransu : can you please answer this doubt which we all have. This
> > we should be able to get from HDA specs.
> >
> >>
> >>> wondering if this approach can cause any issue to subsequent HDA verb
> commands ..
> >>>
> >>>
> >>>> BR,
> >>>> Jani.
> >>>>
> >>>>>>    		min_cdclk = max(2 * 96000, min_cdclk);
> >>>>>>
> >>>>>>    	if (min_cdclk > dev_priv->max_cdclk_freq) {
> >>>>> _______________________________________________
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> >>>>> Intel-gfx at lists.freedesktop.org
> >>>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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> >
> 
> --
> Jani Nikula, Intel Open Source Technology Center