[Intel-gfx] [PATCH] drm/i915: Display WA #1185 WaDisableDARBFClkGating:cnl, glk

[Ville Syrjälä]

On Fri, Nov 10, 2017 at 12:58:50PM -0800, Rodrigo Vivi wrote:
> Display is not sending a PMRsp when a PMReq is received
> at the same time that all planes are turned off.
> State machine in the dcprunit is stuck in the WAIT4DONE
> state which means that there is no fill_done.
> 
> WA: disable arbiter clock gating, set bit [27] of 0x46530
> 
> v2: As Ville pointed out, based on the description the issue
>     can happen when disabling the planes, similar to
>     WaRsPkgCStateDisplayPMReq:hsw
>     Also description of the issue was updated on commit
>     message to make it more clear that we need this
>     earlier.
> v3: Restore comment about possibility to system hang
>     to where we are sure about it, without speculation. (Ville).
> 
> Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

^ double sob

The dangers of adding tags below your sob line and using -s...

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  1 +
>  drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++++++---------
>  2 files changed, 16 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6ef33422f762..fc8c5f8260f6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3819,6 +3819,7 @@ enum {
>   * GEN9 clock gating regs
>   */
>  #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
> +#define   DARBF_GATING_DIS		(1 << 27)
>  #define   PWM2_GATING_DIS		(1 << 14)
>  #define   PWM1_GATING_DIS		(1 << 13)
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5c7540f3f5dc..282a4664a517 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15081,6 +15081,20 @@ get_encoder_power_domains(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +/* System hang if this isn't done before disabling all planes! */
> +static void intel_early_display_was(struct drm_i915_private *dev_priv)
> +{
> +	/* Display WA #1185 WaDisableDARBFClkGating:cnl,glk */
> +	if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> +		I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
> +			   DARBF_GATING_DIS);
> +
> +	/* WaRsPkgCStateDisplayPMReq:hsw */
> +	if (IS_HASWELL(dev_priv))
> +		I915_WRITE(CHICKEN_PAR1_1,
> +			   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
> +}
> +
>  /* Scan out the current hw modeset state,
>   * and sanitizes it to the current state
>   */
> @@ -15094,15 +15108,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>  	struct intel_encoder *encoder;
>  	int i;
>  
> -	if (IS_HASWELL(dev_priv)) {
> -		/*
> -		 * WaRsPkgCStateDisplayPMReq:hsw
> -		 * System hang if this isn't done before disabling all planes!
> -		 */
> -		I915_WRITE(CHICKEN_PAR1_1,
> -			   I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
> -	}
> -
> +	intel_early_display_was(dev_priv);
>  	intel_modeset_readout_hw_state(dev);
>  
>  	/* HW state is read out, now we need to sanitize this mess. */
> -- 
> 2.13.6

-- 
Ville Syrjälä
Intel OTC