[Intel-gfx] [PATCH 1/7] drm/i915/perf: complete whitelisting for OA programming on HSW

[Lionel Landwerlin]

On 13/11/17 11:40, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2017-11-10 19:08:39)
>> We were missing some registers and also can name one for which we only had
>> the offset.
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld at intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_perf.c |  3 ++-
>>   drivers/gpu/drm/i915/i915_reg.h  | 14 ++++++++++++++
>>   2 files changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> index 59ee808f8fd9..45aef15b9e7c 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -3023,7 +3023,8 @@ static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
>>   {
>>          return gen7_is_valid_mux_addr(dev_priv, addr) ||
>>                  (addr >= 0x25100 && addr <= 0x2FF90) ||
>> -               addr == 0x9ec0;
>> +               (addr >= HSW_MBVID2_NOA0.reg && addr <= HSW_MBVID2_NOA9.reg) ||
>> +               addr == HSW_MBVID2_MISR0.reg;
> i915_mmio_reg_offset(HSW_MBVID2_NOA0) etc
> -Chris
>
Oh thanks, will send a follow up patch to clean that up.