[Intel-gfx] [PATCH] drm/i915: Unify SLICE_UNIT_LEVEL_CLKGATE w/a for cnl

[Rafael Antognolli]

On Sat, Nov 11, 2017 at 10:03:36AM +0000, Chris Wilson wrote:
> gem_workarounds reports that the SLICE_UNIT_LEVEL_CLKGATE write isn't
> sticking. Commit 0a60797a0efb ("drm/i915: Implement
> ReadHitWriteOnlyDisable.") presumes that SLICE_UNIT_LEVEL_CLKGATE is a
> masked register in the context image, but commit 90007bca6162
> ("drm/i915/cnl: Introduce initial Cannonlake Workarounds.") lists it as
> an ordering unmasked register. The masked write will be losing the
> default settings if we trust the original commit. That gem_workarounds
> reports the value is lost entirely is more worrying though -- but it
> clearly suggests that it is not a masked register in the context image,
> so unify both w/a to use the original rmw.

Thanks for fixing this.

Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>

> Fixes: 0a60797a0efb ("drm/i915: Implement ReadHitWriteOnlyDisable.")
> References: 90007bca6162 ("drm/i915/cnl: Introduce initial Cannonlake Workarounds.")
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Rafael Antognolli <rafael.antognolli at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Oscar Mateo <oscar.mateo at intel.com>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> Cc: Jani Nikula <jani.nikula at linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 3 ---
>  drivers/gpu/drm/i915/intel_pm.c        | 8 +++++---
>  2 files changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 23694916662f..125e4d90c5f7 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1324,9 +1324,6 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>  	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>  			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>  
> -	/* ReadHitWriteOnlyDisable: cnl */
> -	WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
> -
>  	/* WaEnablePreemptionGranularityControlByUMD:cnl */
>  	I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
>  		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c1a56809f143..6dee6b15f726 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8474,11 +8474,13 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
>  	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>  		   DISP_FBC_MEMORY_WAKE);
>  
> +	val = I915_READ(SLICE_UNIT_LEVEL_CLKGATE);
> +	/* ReadHitWriteOnlyDisable:cnl */
> +	val |= RCCUNIT_CLKGATE_DIS;
>  	/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
>  	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
> -		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,
> -			   I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> -			   SARBUNIT_CLKGATE_DIS);
> +		val |= SARBUNIT_CLKGATE_DIS;
> +	I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, val);
>  
>  	/* Display WA #1133: WaFbcSkipSegments:cnl */
>  	val = I915_READ(ILK_DPFC_CHICKEN);
> -- 
> 2.15.0
>