[Intel-gfx] [PATCH v3 02/11] drm/i915: Remove bogus ips_enabled check.

[Ville Syrjälä]

On Fri, Nov 10, 2017 at 01:57:06PM +0100, Daniel Vetter wrote:
> On Fri, Nov 10, 2017 at 12:34:54PM +0100, Maarten Lankhorst wrote:
> > The flag just tells us IPS can be enabled, if the primary plane
> > is not enabled it means IPS might not be. This never triggered
> > in CI because we don't have a haswell ULT there, but can be
> > reproduced easily with kms_atomic_transitions.plane-all-modeset-transition
> > 
> > Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 4 ----
> >  1 file changed, 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 17665ee06c9a..8d2e1111ef44 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -11258,10 +11258,6 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
> >  		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> >  	}
> >  
> > -	/* BDW+ don't expose a synchronous way to read the state */
> > -	if (IS_HASWELL(dev_priv))
> > -		PIPE_CONF_CHECK_I(ips_enabled);
> 
> Hm ... looking at this ips business I think we got it all wrong. For this
> patch I think you should also remove the hw state readout for ips_enabled
> in haswell_get_pipe_config, it's effectively dead code. With that:

IMO better to fix ips_enabled to account for the active planes.

> 
> Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> 
> > -
> >  	PIPE_CONF_CHECK_I(double_wide);
> >  
> >  	PIPE_CONF_CHECK_P(shared_dpll);
> > -- 
> > 2.15.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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> Intel-gfx at lists.freedesktop.org
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-- 
Ville Syrjälä
Intel OTC